Tag Archives: ASIC Development

Model-Based Design Reduces ASIC Development Time

Semtech, a leading supplier of analog and mixed-signal semiconductors, reduced their ASIC development time by adopting Model-Based Design (with MathWorks MATLAB and Simulink). Using system models for simulation and automatic HDL generation, Semtech engineers created FPGA prototypes 50% faster, reduced verification time from weeks to days, and shortened development time by 33% compared to their previous hand-coded VHDL methodology.

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