By Joe Gianelli and Tom Huang
System integration continues to drive the semiconductor design market. This is most obvious when looking at the increased system integration associated with System on Chip (SoC) design over the last few years. Integrating complex hardware features with complex software applications onto one silicon device makes the validation process for today’s SoC designs a tricky one to say the least.
What have been increasingly popular to aid in this complex validation process are FPGA prototype systems. They run extremely fast, almost as fast as the production SoC, and have doubled in capacity every 18 months for the last 5 years. They also enable real world system interfaces to DDRAM, PCI, Ethernet, while using high-speed serial interfaces over 10 Gb/s.
Despite their current strides in speed, capacity, and real world high-speed interfaces, using these FPGA devices to help verify and validate SoC designs are difficult at best due to the many and long FPGA P&R compile times and poor visibility. InPA Systems proposes to address these issues with their active debug and full visibility technology.