Synopsys DesignWare System-Level Library
Synopsys, Inc. (NASDAQ: SNPS) recently announced the DesignWare(R) System-Level Library. The library provides high-performance SystemC transaction-level simulation models (TLMs) for assembling virtual platforms, including instruction set simulators (ISS), and TLMs of Synopsys' DesignWare Cores and ARM(R) AMBA(R) interconnect components. All DesignWare System-Level Library models are written in SystemC and work in IEEE 1666 (SystemC) compliant […]
Micro Magic MAX-3D 3D Layout Editor
MAX-3D, from Micro Magic, is a true 3D-aware layout editor. MAX-3D can combine distinct process wafers, and allows the designer to view, edit, and connect the independent wafers into one 3D stack chip. The design technique — known as "Through-Si Via Wafer Stacking" — is a new dimension for chip designs. It allows distinct wafers […]
Cypress PSoC FirstTouch Starter Kit
Cypress Semiconductor's (NYSE:CY) PSoC(R) FirstTouch(TM) Starter Kit is a USB thumbdrive kit that provides a quick, easy, and affordable way for embedded designers to evaluate the integration, flexibility, and real mixed-signal programmability of PSoC mixed-signal arrays. Without writing or debugging a single line of C or Assembly code, the PSoC FirstTouch Starter Kit provides designers […]
Cadence SoC Functional Verification Kit
The Cadence (NASDAQ: CDNS) SoC Functional Verification Kit is a comprehensive verification kit for wireless and consumer system-on-chip (SoC) design. It enables engineers to adopt advanced verification techniques with reduced risk and deployment effort and meet time-to-market requirements. The Cadence(R) SoC Functional Verification Kit provides a proven end-to-end methodology that extends from block-level verification to […]
Ardence Select 2.0
Ardence recently released Select 2.0, which includes support for the Windows Vista operating system and enables OEMs to deliver Vista-based devices with multi-purpose functionality on a single operating system as well as provide instant-on/instant-off capability. Select will reduce OEMs' time, effort, and expense in creating multi-functional Vista-based devices. With Select, system configurations can be instantly […]
Empower LDK6446 LEOs Development Kit
Empower Technologies' (TSX.V: EPT) latest LEOs Development Kit (LDK6446) is designed for Texas Instruments' (TI) DM6446 DaVinci(TM) Technology dual-core embedded CPU. DM6446 is a DaVinci(TM) Processor which forms part of TI's DaVinci(TM) Technology ecosystem. The technology includes the following elements: DaVinci Software, DaVinci Development Tools/Kits, and DaVinci Support. The new LDK6446 development kit comes with […]
Cypress PSoC Express 3.0
Cypress Semiconductor Corp. (NYSE:CY) PSoC Express(TM) 3.0 delivers real-time monitoring and tuning of designs. PSoC Express is a visual embedded system design tool for PSoC(R) mixed-signal arrays. The tool enables designers to observe and improve the performance of designs with Cypress's CapSense(TM) touch sensing and EZ-Color(TM) High-Brightness LED (HB-LED) control solutions.
Designers can now monitor application […]
EnOcean EVA 120C Evaluation Kit
EnOcean's EVA 120C Evaluation Kit includes everything necessary to quickly develop and test ultra low power wireless sensor modules for a variety of electrical and electronics applications. The kit components include an EnOcean STM 110C solar powered sensor transmitter module and a development board with a PC interface. Detailed technical documentation, including data sheet, manual […]
Avery Design PCI-Xactor for PCI Express Gen2
PCI-Xactor for PCI Express, from Avery Design Systems, provider of industry proven Verification IP for PCI Express and Parallel/Serial ATA, offers comprehensive coverage on the digital logic portion of the PCI–SIG Protocol Checklist. PCI-Xactor for PCI Express 2.0 (Gen2) is for functional verification of PCI Express designs.
The new release fully supports Gen2 including Root Complex, […]
TED Virtex-5 LX Multi-Application Evaluation Platform
Tokyo Electron Device (TED) has developed a multi-application evaluation platform for the Xilinx(R) Virtex-5 LX 330 FPGA family. TED's Virtex-5 LX Multi-Application Evaluation Platform enables efficient design and evaluation of a wide range of high-speed applications, including consumer products such as high definition televisions, set-top boxes and printers, as well as telecommunications equipment, medical […]
Mentor Graphics PADS2007 PCB Design Solution
Mentor Graphics (Nasdaq: MENT) PADS2007 offers layout designers and engineers the ability to implement RF and microwave circuitry using highly automated functionality, perform design for fabrication (DFF) checking early in the design process, and optimize performance with advanced high-speed analysis/verification functionality, thus significantly improving their productivity and design quality. PADS is a Windows(R)-based PCB design […]
Sigrity OptimizePI Power Delivery System
Sigrity's OptimizePI is a next-generation Power Delivery System (PDS) solution that is the first to provide minimum-cost decoupling capacitor (decap) selection and placement to achieve desired PDS performance. OptimizePI is based on Sigrity's analysis and verification capabilities for the entire PCB and IC package structure. It lets designers assess PDS performance against design specifications, make […]
STMicroelectronics STR750 Motor Control Starter Kit
The STR750 Motor Control Starter Kit, from STMicroelectronics (NYSE: STM), is built around the 32-bit STR750 microcontroller, which enables the rapid development of high-performance vector-control applications, using both Permanent Magnet Synchronous Motors (PMSM) and 3-phase AC Induction Motors, for cost-sensitive appliance, industrial and HVAC (heating, ventilation and air conditioning) markets. The kit includes all the […]
Tensilica Xenergy Energy Estimator Tool
The Xenergy(TM) estimator is an energy estimator for both Xtensa(R) configurable processor and Diamond Standard processor users. By using the Xenergy tool to optimize for energy early in the SOC (System On Chip) design cycle, designers can cut processor and local memory energy requirements by up to half by making intelligent design trade-offs. Total energy […]
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