Category Archives: IP Core

ip, cores

Mentor Graphics SATA/Device Host Device IP Controller

Mentor Graphics Corporation (Nasdaq: MENT) recently updated Serial ATA (SATA) Host/Device Intellectual Property (IP) controllers with added support for the most commonly used features in the latest SATA specification, Revision 2.6. Including support for features such as Native Command Queuing and Asynchronous Notification, Mentor is ensuring their customers will continue reducing time to market with storage-based products, including hard and optical disk drives, network storage applications and consumer electronics. The updated SATA Host/Device controllers are available for immediate delivery.

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SNOWBUSH microelectronics’ 6-bit, 2.5 GSPS ADC IP core is ideal for the most demanding data-conversion applications. The ADC is compact, low-power, and by utilizing its high bandwidth sample-and-hold front-end, it maintains excellent dynamic performance throughout the full range of input frequencies. The ADC features INL of 0.59 LSB, DNL of 0.51 LSB, and ENOB of 5.2 or greater for sampling clock frequencies up to 2.5 GHz. The ADC occupies a silicon area of 0.43 square millimeters.

The state-of-the-art ADC utilizes automatic calibration of key analog blocks to ensure performance over variations in process, voltage, and temperature. The ADC features on-chip power-supply regulation for robust noise immunity within large digital SOC’s. Several power-down modes are provided to minimize power consumption.

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Lattice DDR2 SDRAM Controller IP Core

Lattice’s (NASDAQ: LSCC) 533 Mbps DDR2 SDRAM IP core is optimized for the LatticeECP2(TM) and LatticeECP2M(TM) low-cost FPGA families, as well as its high-end LatticeSC(TM) Extreme Performance(TM) FPGA family.

The Double Data Rate Synchronous Dynamic Random Access Memory Controller IP core interfaces seamlessly with industry standard DDR2 SDRAM memory devices and has been performance-tuned for Lattice FPGAs. Not only does this IP core support all DDR2 commands, it also is extremely flexible, with intelligent bank management to minimize active commands, a synchronous implementation for reliable operation and a command pipeline to maximize throughput. The most common memory configurations are supported through a combination of variable address widths for different memory devices, programmable timing parameters, byte level writing through data mask signals and burst termination.

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Arasan IP Cores for Mobile Industry Processor Interface

Arasan offers a suite of IP Cores that support the emerging MIPI(TM) (Mobile Industry Processor Interface) standards. The new products available include the Display Serial Interface (DSI) IP Core, the Camera Serial Interface (CSI-2) IP Core, and the D-PHY IP Core. The SLIMbus(TM) IP Core (Serial Low-power Inter-chip Media bus) supporting the preliminary draft specification is also available. In addition to the hardware IP, Arasan provides Software drivers and stacks for a number of the interface protocols. Also available is a separate set of Verification IP including bus functional models and tests that can be used to validate the operation of the IP in a unit test and systems environment. Each test platform comes with a set of directed tests designed to exercise the elements of the protocol.

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LatticeECP2M PCI Express x4 IP Core

Lattice Semiconductor (NASDAQ: LSCC) LatticeECP2M PCI Express x4 IP core is optimized for the LatticeECP2M(TM) low-cost FPGA family. Like the previous PCI Express x1 IP core for LatticeECP2M devices, the x4 version implements a single-chip PCI Express endpoint solution with integrated SERDES that is ideal for high-volume, low-cost and limited form-factor applications.

Lattice’s PCI Express x4 solution includes the IP core, an evaluation board, demonstration software, and drivers. Lattice is the only FPGA supplier to offer single-chip PCI Express solutions with on-board SERDES in both low-cost (LatticeECP2M) and high-end (LatticeSCM(TM)) FPGAs. LatticeECP2M and LatticeSCM evaluation boards are both available in the PCI Express mechanical form-factor compatible with standard motherboards. The demo software utilizes the evaluation boards to demonstrate PCI express endpoint operation, including configuration, memory/register access and simple tests. Demo drivers and API also are available for users who wish to extend the demo capabilities.

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Actel CoreABC and Core8051s Controller Cores

Actel recently introduced the small, easy-to-use CoreABC and the configurable Core8051s. The controller cores complement the company’s existing library of industry-standard options, including a variety of ARM, 8051 and LEON processor solutions, optimized for Actel’s field-programmable gate arrays (FPGAs). In addition to third-party tools and capabilities, Actel also offers a comprehensive development environment, boards and reference designs to support its processor offerings. This ecosystem of tools and support enable Actel customers to get system-level products to market quickly and reduce cost and risk.

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SLE Interlaken Interconnect Protocol IP Core

Silicon Logic Engineering has a licensable Interlaken protocol IP core for use in ASIC or FPGA designs. Their Interlaken IP Core is scalable, with early versions providing from 10 Gbps to 60+ Gbps bandwidth across the interface. Future versions will provide over 120Gbps of bandwidth. This scalability ideally suits Interlaken for multiple generations of future network switches, routers and storage equipment. The scalability is achieved through the combination of the SERDES speed (3.125Gbps to 6.375Gbps) and a variable number of SERDES lanes (1 to 24).

Designed and tested to be easily synthesizable into many ASIC and FPGA technologies, SLE’s Interlaken IP Core was uniquely built to work with off-the-shelf SERDES from most leading technology vendors. Using the vendor specific proven SERDES allows SLE customers to quickly integrate the Interlaken IP Core into the customer’s technology of choice.

The open Interlaken specification was co-written by Cortina Systems and Cisco Systems to provide a far more scalable chip-to-chip interface protocol than previous protocols. Interlaken combines the advantages of the popular SPI4.2 and XAUI interfaces by building on the channelization and per channel flow control features of SPI4.2, and reducing the number of chip I/O pins by using high speed SERDES technology, similar to XAUI.

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