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'IP Core' Category Archive

Tensilica ConnX DSP Family of Communications IP Cores

Posted by Ken Cheung in DSP,IP Core on Monday, June 22, 2009

The ConnX DSP, from Tensilica, is a family of high-performance communications DSP (digital signal processors) IP (intellectual property) cores. The ConnX DSPs feature standard cores, click-box configurable options or a starting point for customized Xtensa® LX DPUs (dataplane processor units) for SOC (system-on-chip) designs. The new pre-designed communications DSP cores enables designers to achieve faster [...]

Fast Fourier Transform and FIR Filter Compiler DSP IP Cores

Posted by Ken Cheung in DSP,FPGA,IP Core on Wednesday, May 6, 2009

eASIC introduced two new DSP IP cores, an FFT and FIR Filter Compiler. The FT core supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint. The FIR Compiler core (available from Steepest Ascent) can process data streams as high as 500 MSPS and is ideal [...]

RTXC Quadros Real-time Operating Systems Support ARM1136, ARM1176 Cores

Posted by Ken Cheung in IP Core,Microcontrollers,RTOS on Monday, April 20, 2009

Quadros Systems announced that their RTXC Quadros Real-time Operating Systems (RTOS) now support ARM1136 and ARM1176 cores from ARM. The RTXC Quadros RTOS offers a small footprint and excellent efficiency while ARM11 processors deliver high performance and low energy consumption. The combination of RTXC Quadros RTOS and ARM11 processors is ideal for consumer electronics, GPS [...]

ARM Cortex-M0 Processor

Posted by Ken Cheung in IP Core on Tuesday, February 24, 2009

ARM introduced their Cortex-M0 processor. The Cortex-M0 is the smallest, lowest power, and most energy-efficient ARM processor available. The low power, small gate count, and code footprint of the processor enables MCU developers to achieve 32-bit performance at an 8-bit price point. The ultra low gate count makes it ideal for analog and mixed signal [...]

Virage Logic emPROM Memory System

Posted by Ken Cheung in IP Core,Reference Design on Tuesday, September 30, 2008

The emPROM Memory System, from Virage Logic Corporation (NASDAQ:VIRL), is a family of embedded multi-time programmable (MTP) non-volatile memory (NVM) for flexible program code storage in System-on-Chip (SoC) devices. Combining user-defined functionality with Virage Logic’s high-capacity read-only memory (ROM) and NOVeA Flash memory, emPROM provides secure, fully integrated embedded NVM for SoC designs requiring up [...]

MIPS MIPS32 1004K Multiprocessor IP Core

Posted by Ken Cheung in IP Core on Monday, June 30, 2008

The MIPS32 1004K coherent processing system, from MIPS Technologies, Inc. (NasdaqGS: MIPS), is the industry’s first embedded multi-threaded, multi-processor licensable IP core. The multi-core offers efficiency and configurability in a multi-processing system up to four single or multi-threaded processors integrated with advanced system coherency. The 1004K core optimizes CPU performance on a shared memory system, [...]

Mentor Graphics SATA/Device Host Device IP Controller

Posted by Ken Cheung in IP Core on Thursday, March 6, 2008

Mentor Graphics Corporation (Nasdaq: MENT) recently updated Serial ATA (SATA) Host/Device Intellectual Property (IP) controllers with added support for the most commonly used features in the latest SATA specification, Revision 2.6. Including support for features such as Native Command Queuing and Asynchronous Notification, Mentor is ensuring their customers will continue reducing time to market with [...]

SNOWBUSH ADC IP Core

Posted by Ken Cheung in IP Core on Monday, October 8, 2007

SNOWBUSH microelectronics’ 6-bit, 2.5 GSPS ADC IP core is ideal for the most demanding data-conversion applications. The ADC is compact, low-power, and by utilizing its high bandwidth sample-and-hold front-end, it maintains excellent dynamic performance throughout the full range of input frequencies. The ADC features INL of 0.59 LSB, DNL of 0.51 LSB, and ENOB of [...]

Lattice DDR2 SDRAM Controller IP Core

Posted by Ken Cheung in FPGA,IP Core on Wednesday, August 15, 2007

Lattice’s (NASDAQ: LSCC) 533 Mbps DDR2 SDRAM IP core is optimized for the LatticeECP2(TM) and LatticeECP2M(TM) low-cost FPGA families, as well as its high-end LatticeSC(TM) Extreme Performance(TM) FPGA family. The Double Data Rate Synchronous Dynamic Random Access Memory Controller IP core interfaces seamlessly with industry standard DDR2 SDRAM memory devices and has been performance-tuned for [...]

Arasan IP Cores for Mobile Industry Processor Interface

Posted by Ken Cheung in IP Core,Wireless on Wednesday, August 8, 2007

Arasan offers a suite of IP Cores that support the emerging MIPI(TM) (Mobile Industry Processor Interface) standards. The new products available include the Display Serial Interface (DSI) IP Core, the Camera Serial Interface (CSI-2) IP Core, and the D-PHY IP Core. The SLIMbus(TM) IP Core (Serial Low-power Inter-chip Media bus) supporting the preliminary draft specification [...]

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