Tensilica announced the Xtensa LX3 high-performance dataplane processor (DPU) core. The Xtensa LX3 DPU is optimized for digital signal processing (DSP) and control in the system-on-chip (SOC) dataplane. The Xtensa LX3 DPU offers a wide range of pre-verified DSP options ranging from a simple floating point accelerator to a 16-MAC (multiply accumulator) vector DSP powerhouse. The Xtensa LX3 customizable DPU is available now.
Tata Elxsi’s RoS-ES (Real Time Operating System for Embedded Systems) operating system is now available for Tensilica’s Xtensa customizable dataplane processors (DPUs) and Diamond Standard processors. Tensilica’s processor cores are efficient and, when paired with our RoS-ES RTOS, they become effective SOC controllers. Tata Elxsi’s RoS-ES is a compact real-time operating system (RTOS) that provides an array of capabilities. Roses Embedded Operating System is ideal for networking and consumer electronics applications.
ARM developed two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process. The hard macro implementations enable silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz. The Cortex-A9 hard macros and the corresponding optimized physical IP used to develop the speed-optimized and power-optimized implementations are available for license today with delivery in the fourth quarter of 2009.
The ARM 0.18µm ultra low power libraries (uLL), coupled with the inherent power management advantages of the ARM Cortex processor family and the TSMC 0.18µm embedded flash uLL/HDR high data retention process provides SoC designers with additional reduction in power leakage up to 10x compared to 0.18um G implementations. ARM 0.18µm ultra low-power physical IP libraries is available now.
The ConnX DSP, from Tensilica, is a family of high-performance communications DSP (digital signal processors) IP (intellectual property) cores. The ConnX DSPs feature standard cores, click-box configurable options or a starting point for customized Xtensa® LX DPUs (dataplane processor units) for SOC (system-on-chip) designs. The new pre-designed communications DSP cores enables designers to achieve faster time-to-market on next-generation of communications SOCs.
eASIC introduced two new DSP IP cores, an FFT and FIR Filter Compiler. The FT core supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint. The FIR Compiler core (available from Steepest Ascent) can process data streams as high as 500 MSPS and is ideal for Nextreme and Nextreme-2 architectures. The new DSP blocks enable wireless and video/imaging system designers to rquickly migrate costly FPGA-based DSP designs to lower-cost, lower-power Nextreme Series NEW ASICs.
Quadros Systems announced that their RTXC Quadros Real-time Operating Systems (RTOS) now support ARM1136 and ARM1176 cores from ARM. The RTXC Quadros RTOS offers a small footprint and excellent efficiency while ARM11 processors deliver high performance and low energy consumption. The combination of RTXC Quadros RTOS and ARM11 processors is ideal for consumer electronics, GPS systems, and product that needs fast interrupt processing and high data throughput.
ARM introduced their Cortex-M0 processor. The Cortex-M0 is the smallest, lowest power, and most energy-efficient ARM processor available. The low power, small gate count, and code footprint of the processor enables MCU developers to achieve 32-bit performance at an 8-bit price point. The ultra low gate count makes it ideal for analog and mixed signal devices and MCU applications. The ARM Cortex-M0 is available for licensing today.
The emPROM Memory System, from Virage Logic Corporation (NASDAQ:VIRL), is a family of embedded multi-time programmable (MTP) non-volatile memory (NVM) for flexible program code storage in System-on-Chip (SoC) devices. Combining user-defined functionality with Virage Logic’s high-capacity read-only memory (ROM) and NOVeA Flash memory, emPROM provides secure, fully integrated embedded NVM for SoC designs requiring up to 16 Megabits of code storage and is manufactured on industry standard CMOS processes with no additional mask or process steps. Virage Logic’s emPROM Memory System is available now along with a 90nm reference design. The reference design includes a project license for a 1Mbit Via ROM, 4Kbit NOVeA 3.0, emPROM processor, RTL source code and documentation. emPROM pricing starts at $90,000.
The MIPS32 1004K coherent processing system, from MIPS Technologies, Inc. (NasdaqGS: MIPS), is the industry’s first embedded multi-threaded, multi-processor licensable IP core. The multi-core offers efficiency and configurability in a multi-processing system up to four single or multi-threaded processors integrated with advanced system coherency. The 1004K core optimizes CPU performance on a shared memory system, enabling multiple functions and applications to be implemented in a single product-all running concurrently and responsively under symmetric multiprocessing (SMP)-based operating systems.