Embedded Star » IP Core

Tensilica ConnX BBE64-128 and BBE64-UE DSP IP Cores

Ken Cheung — Tue, 08 Feb 2011 15:31:29 +0000

Tensilica introduced the ConnX BBE64-128 and BBE64-UE DSP (digital signal processor) IP (intellectual property) cores for SOC (system-on-chip) design. The ConnX BBE64-128 IP core features 100+ GigaMACs performance in 28nm high-performance process technology. The ConnX BBE64-UE is optimized for the low power and small area requirements of LTE Advanced handsets. An evaluation kit for the ConnX BBE64-128 and ConnX BBE64-UE cores is expected to be available in the fall of 2011.

Twitter @embeddedstar : : Free Publications : : Jobs : : Embedded Star : : FPGA Blog : : EDA Geek : : EDA Blog :: Dad Blog
© 2011 Online Destiny Ltd : : Embedded Star is a trademark of Online Destiny Ltd

MIPS32 1074K Coherent Processing System

Ken Cheung — Wed, 29 Sep 2010 11:01:19 +0000

MIPS Technologies announced the MIPS32 1074K Coherent Processing System (CPS). The new processor is a fully-synthesizable multicore IP that approaches production frequencies of 1.5 GHz in 40nm G process. The MIPS 1074K CPS will be available in October 2010. Two initial versions of the 1074K CPS will be available: the MIPS32 1074Kc CPS, which provides a coherent processing system using base integer cores, and the MIPS32 1074Kf CPS, which includes a floating point unit (FPU) in each core.

Twitter @embeddedstar : : Free Publications : : Jobs : : Embedded Star : : FPGA Blog : : EDA Geek : : EDA Blog :: Dad Blog
© 2010 Online Destiny Ltd : : Embedded Star is a trademark of Online Destiny Ltd

Novelics coolSRAM-6T Embedded Memory IP and MemQuest Compiler

Ken Cheung — Tue, 14 Sep 2010 11:05:03 +0000

Novelics introduced the coolSRAM-6T embedded memory IP and MemQuest compiler, which are enhanced with Novelics 3G optimizations. The coolSRAM-6T IP is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs. The coolSRAM-6T enables ASSP and ASIC designers to achieve higher performance and more power-efficient system-on-chips (SoCs). The SRAM-6T in 40nm is available for licensing now. The initial offering is offered in TSMC’s 40nm GP / LP technologies. Support for UMC, GF, and SMIC will also be offered.

DarbeeVision DV3000 Visual Presence IP Core

Ken Cheung — Wed, 02 Jun 2010 23:00:31 +0000

DarbeeVision introduced the DV3000 Visual Presence IP core. The DV3000 inserts depth cues to create images that seem to pop off the screen. The DV3000 improves images by using digital logic to process an image in the same way a human brain does and then adding these results back into the original image, making them better than what the most camera and display systems can produce. The DV3000 IP core is now available for licensing.

Evatronix R80251XC 32-bit Intel 80C251 Microcontroller IP Core

Ken Cheung — Mon, 24 May 2010 17:24:29 +0000

Evatronix introduced the R80251XC 32-bit Intel 80C251 compatible microcontroller. The 8051 compatible IP core exceeds the original Intel 8051 chip by more than 24 times (over 3 times better result than the Intel 80C251 at the same clock frequency). The Evatronix R80251XC IP core is available for licensing now. The core includes synthesis and simulation support scripts Verilog or VHDL test bench, and a reference design for the proprietary evaluation board.

Express Logic ThreadX/SMP RTOS

Ken Cheung — Mon, 26 Apr 2010 21:26:57 +0000

Express Logic introduced ThreadX/SMP RTOS for the MIPS32 1004K Coherent Processing System (CPS). ThreadX/SMP is an enhanced version of ThreadX. It provides synchronous multicore support that preserves real-time responsiveness called Real-Time SMP. ThreadX/SMP enables developers to take advantage of the performance boost of sharing the processing load over the multiple processor cores of the 1004K CPS while maintaining the real-time responsiveness critical to demanding embedded applications. ThreadX/SMP is available in full source code form, royalty-free, with project license prices starting at $15,500.

DDC-I Deos RTOS Supports Freescale e300 and e500 Cores

Ken Cheung — Thu, 15 Apr 2010 11:06:27 +0000

The Deos real-time operating system and OpenArbor development tool suite are now available for the Freescale Semiconductor e300 and e500 cores. Deos running on the PowerQUICC II Pro and PowerQUICC III processors is an ideal platform for developing and hosting mil/aero and other safety-critical applications — especially those requiring high design assurance and timely DO-178B certification.

Virage Logic ARC 601 32-bit Microprocessor Core

Ken Cheung — Wed, 16 Dec 2009 12:02:58 +0000

Virage Logic introduced the ARC 601 32-bit microprocessor core. The ARC 601 runs at 532MHz (1.2 DMIPS/MHz) and consumes only 13 µW/MHz in 65-nanometer (nm) process technology. The IP core is only 0.039 mm² in size and will fit 2.5 times into the size of the dot (12 point font) at the end of a sentence. The processor is available now and has already been licensed to several of Virage Logic’s lead customers. The core is targeted at audio, imaging, portable, storage, consumer, wireless, and security applications.

Twitter @embeddedstar : : Free Publications : : Jobs : : Embedded Star : : FPGA Blog : : EDA Geek : : EDA Blog :: Dad Blog
© 2009 Online Destiny Ltd : : Embedded Star is a trademark of Online Destiny Ltd

MIPS M14K Microcontroller Core Family

Ken Cheung — Mon, 02 Nov 2009 19:08:58 +0000

MIPS Technologies launched the M14K core family for extremely cost-sensitive embedded applications. The MIPS32 M14K and M14Kc cores are the first MIPS32 compatible cores that also execute the new microMIPS instruction set architecture (ISA), achieving high performance of 1.5 DMIPS/MHz with an advanced level of code compression. The microMIPS ISA maintains 98% of MIPS32 performance while reducing code size by 35%, translating to significant silicon cost savings. The M14K cores are ideal for 32-bit microcontrollers (MCUs), home entertainment, personal entertainment, and home networking. The new M14K and M14Kc cores will be available in the first quarter of 2010.

Tensilica Tensa LX3 Customizable Dataplane Processor Core

Ken Cheung — Mon, 02 Nov 2009 16:20:09 +0000

Tensilica announced the Xtensa LX3 high-performance dataplane processor (DPU) core. The Xtensa LX3 DPU is optimized for digital signal processing (DSP) and control in the system-on-chip (SOC) dataplane. The Xtensa LX3 DPU offers a wide range of pre-verified DSP options ranging from a simple floating point accelerator to a 16-MAC (multiply accumulator) vector DSP powerhouse. The Xtensa LX3 customizable DPU is available now.