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'IP Core' Category Archive

DarbeeVision DV3000 Visual Presence IP Core

Posted by Ken Cheung in IP Core on Wednesday, June 2, 2010

DarbeeVision introduced the DV3000 Visual Presence IP core. The DV3000 inserts depth cues to create images that seem to pop off the screen. The DV3000 improves images by using digital logic to process an image in the same way a human brain does and then adding these results back into the original image, making them [...]

Evatronix R80251XC 32-bit Intel 80C251 Microcontroller IP Core

Posted by Ken Cheung in IP Core,Microcontrollers on Monday, May 24, 2010

Evatronix introduced the R80251XC 32-bit Intel 80C251 compatible microcontroller. The 8051 compatible IP core exceeds the original Intel 8051 chip by more than 24 times (over 3 times better result than the Intel 80C251 at the same clock frequency). The Evatronix R80251XC IP core is available for licensing now. The core includes synthesis and simulation [...]

Express Logic ThreadX/SMP RTOS

Posted by Ken Cheung in IP Core,RTOS on Monday, April 26, 2010

Express Logic introduced ThreadX/SMP RTOS for the MIPS32 1004K Coherent Processing System (CPS). ThreadX/SMP is an enhanced version of ThreadX. It provides synchronous multicore support that preserves real-time responsiveness called Real-Time SMP. ThreadX/SMP enables developers to take advantage of the performance boost of sharing the processing load over the multiple processor cores of the 1004K [...]

DDC-I Deos RTOS Supports Freescale e300 and e500 Cores

Posted by Ken Cheung in IP Core,Microcontrollers,RTOS on Thursday, April 15, 2010

The Deos real-time operating system and OpenArbor development tool suite are now available for the Freescale Semiconductor e300 and e500 cores. Deos running on the PowerQUICC II Pro and PowerQUICC III processors is an ideal platform for developing and hosting mil/aero and other safety-critical applications — especially those requiring high design assurance and timely DO-178B [...]

Virage Logic ARC 601 32-bit Microprocessor Core

Posted by Ken Cheung in IP Core,Microcontrollers on Wednesday, December 16, 2009

Virage Logic introduced the ARC 601 32-bit microprocessor core. The ARC 601 runs at 532MHz (1.2 DMIPS/MHz) and consumes only 13 µW/MHz in 65-nanometer (nm) process technology. The IP core is only 0.039 mm2 in size and will fit 2.5 times into the size of the dot (12 point font) at the end of a [...]

MIPS M14K Microcontroller Core Family

Posted by Ken Cheung in IP Core,Microcontrollers on Monday, November 2, 2009

MIPS Technologies launched the M14K core family for extremely cost-sensitive embedded applications. The MIPS32 M14K and M14Kc cores are the first MIPS32 compatible cores that also execute the new microMIPS instruction set architecture (ISA), achieving high performance of 1.5 DMIPS/MHz with an advanced level of code compression. The microMIPS ISA maintains 98% of MIPS32 performance [...]

Tensilica Tensa LX3 Customizable Dataplane Processor Core

Posted by Ken Cheung in IP Core on Monday, November 2, 2009

Tensilica announced the Xtensa LX3 high-performance dataplane processor (DPU) core. The Xtensa LX3 DPU is optimized for digital signal processing (DSP) and control in the system-on-chip (SOC) dataplane. The Xtensa LX3 DPU offers a wide range of pre-verified DSP options ranging from a simple floating point accelerator to a 16-MAC (multiply accumulator) vector DSP powerhouse. [...]

RoS-ES RTOS for Diamond Standard and Xtensa Customizable DPUs

Posted by Ken Cheung in IP Core,RTOS on Thursday, October 15, 2009

Tata Elxsi’s RoS-ES (Real Time Operating System for Embedded Systems) operating system is now available for Tensilica’s Xtensa customizable dataplane processors (DPUs) and Diamond Standard processors. Tensilica’s processor cores are efficient and, when paired with our RoS-ES RTOS, they become effective SOC controllers. Tata Elxsi’s RoS-ES is a compact real-time operating system (RTOS) that provides [...]

ARM Cortex-A9 MPCore Hard Macro Implementations

Posted by Ken Cheung in IP Core on Thursday, September 17, 2009

ARM developed two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process. The hard macro implementations enable silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz. The Cortex-A9 hard macros and [...]

ARM .18um Ultra Low Power Libraries

Posted by Ken Cheung in IP Core on Tuesday, July 28, 2009

The ARM 0.18µm ultra low power libraries (uLL), coupled with the inherent power management advantages of the ARM Cortex processor family and the TSMC 0.18µm embedded flash uLL/HDR high data retention process provides SoC designers with additional reduction in power leakage up to 10x compared to 0.18um G implementations. ARM 0.18µm ultra low-power physical IP [...]

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