The Altera(R) Automotive Graphics System (AAGS) is a scalable solution that enables design engineers to quickly and efficiently design multiple automotive infotainment products based on a single electronic design. Implemented in Altera’s low-cost Cyclone(R) series or high-performance Stratix(R) series FPGAs, the AAGS enables designers to overcome the lengthy and costly design cycles of fixed-function graphic controllers.
Xilinx Virtex-4 QPRO MIL-grade FPGAs are designed for the aerospace and defense industry. The Virtex-4 QPRO FPGAs provides the industry’s most comprehensive ‘space to base’ device portfolio with higher performance, lower power options, and full military temperature-qualification. The new Virtex-4 QPRO family builds on the existing Virtex-II QPRO device offering, which includes the industry’s first military temperature-qualified FPGA with an embedded processor core, introduced in January 2005.
OneSpin Solutions GmbH’s 360 EC-FPGA equivalence checking solution supports all sequential optimizations performed by FPGA synthesis tools on large designs, enabling designers to meet functional, performance and cost targets, with minimal manual intervention. It is ideal for both prototyping and production-part verification. The new 360 EC-FPGA enhances OneSpin’s established 360 EC ASIC equivalence checker with innovative FPGA verification capability. It thoroughly proves, without simulation, that design functionality is maintained through all implementation phases of FPGA and ASIC design.
The Xilinx 65nm Virtex(TM)-5 SXT field programmable gate arrays (FPGAs) are optimized for high-performance digital signal processing (DSP). The SXT platform establishes an industry record for DSP performance delivering 352 GMACs at 550MHz, while consuming 35 percent less dynamic power as compared to previous 90nm generation devices, and is the first DSP-optimized FPGA family to integrate serial transceivers.
The Virtex-5 SXT platform delivers the highest ratio of DSP blocks-to-logic needed for high-performance digital signal processing applications in wireless, such as WIMAX and high-definition video, such as surveillance and broadcast. The enhanced DSP slice (DSP48E) includes a 25×18-bit multiplier, a 48-bit second stage for accumulation and arithmetic operations, and a 48-bit output that can be expanded to 96-bits. The wider data path and output enable increased dynamic range and higher precision as well as optimized support for single precision floating point operations using half the resources consumed by 90-nm FPGAs.
Xilinx’s Integrated Software Environment (ISE(TM)) WebPACK(TM) 9.1i is the latest version of the company’s free downloadable programmable logic design suite. The new version includes all the features of the 9.1i release of the popular Xilinx ISE Foundation(TM) software with full support for optional embedded, digital signal processing (DSP) and real-time debug design flows. Most notably, ISE WebPACK 9.1i software includes the new Xilinx SmartCompile(TM) technology, which significantly improves run times by up to 6x faster than the previous version, while maintaining exact design preservation of unchanged logic.
The Aldec Active-HDL Lattice Designer Edition Lite is a FPGA design tool. It supports mixed VHDL and Verilog simulation for Lattice’s leading FPGA devices, including the 90nm Extreme Performance(TM) LatticeSC(TM) family as well as the 90nm LatticeECP2M(TM) family, which is the industry’s only low-cost FPGA family with unequaled on-chip memory capacity and 3.125 Gbps SERDES I/O.
In addition to mixed VHDL and Verilog RTL and Timing Simulation, Active-HDL Lattice Designer Edition Lite also will include Aldec’s HDL Text Editor, Language Assistant, State Machine Editor, Block Diagram Editor and other point tools in a single design workspace. Key debug capabilities such as Code Execution Tracing and Advanced Breakpoint Management also are included in the Lattice edition.
Price and Availability
Active-HDL Lattice Designer Edition Lite is available from Lattice now. The list price of $1249 for an annual node-locked license makes the Active-HDL Lattice Designer Edition Lite the industry’s superior mixed-language simulator value.
The Atmel ATF15xxBE family of ROHS-compliant, 1.8V CPLDs feature standby power consumption of just 5 uA — over 60% less power drain than the nearest competing CPLD. Operating power consumption is 1 mA at 20 MHz or less. Available in densities ranging from 32 to 128 macrocells, ATF15xxBE CPLDs can be used to implement system watchdog, MCU I/O port expansion, memory interface, LCD display module drivers, and voltage translators.
Their ultra-low standby power consumption makes the ATF15xxBE PLDs ideal for applications that spend the majority of their time in standby mode. These include smart phones, keypad scanners, and handheld appliances as well as toys using infrared transmitters with low security needs.
The Xilinx Spartan(TM)-3A family of I/O-optimized field programmable gate arrays (FPGAs) is an extension of its low-cost, high volume Spartan-3 Generation. The Spartan-3A platform provides a cost-reduced solution for applications where I/O count and capabilities matter more than logic density. With support for the industry’s widest range of I/O standards (26) and unique power, configuration capabilities and anti-cloning security advantages, Spartan-3A FPGAs provide a flexible and cost-saving solution to new high-volume applications within consumer and industrial segments, such as display panel interfaces, video/tuner board interfaces and video switching.
Built on 90nm technology, the new platform consists of five devices offering up to 1.4 million system gates and 502 I/Os. Offering the lowest cost per I/O in the industry, the new family also features significant advances in power management, device configuration and design security. The Spartan-3A platform integrates an impressive array of innovative features and technologies including:
Altera(R) Stratix III FPGAs feature two new technologies that dramatically lower power while meeting high-performance requirements. Reduced power consumption is achieved by utilizing Altera’s innovative Programmable Power Technology, which maximizes performance where needed while delivering the lowest power elsewhere in the design. Programmable Power Technology enables every programmable logic array block (LAB), DSP block and memory block to independently operate at high-speed or low-power mode.
The PowerPlay feature in Quartus II software version 6.1 automatically analyzes the design and identifies which blocks are in the critical path and demand the highest performance, setting these to high-speed mode. All other logic is automatically put into low-power mode. The second power-optimizing feature, Selectable Core Voltage, provides the designer options to select either 1.1V for designs needing the highest performance or 0.9V for designs requiring minimum power consumption.
Aeroflex RadHard Eclipse FPGA offers proven commercial architecture, guaranteed radiation performance and reliability, an efficient low power, high performance FPGA fabric coupled with embedded RadHard SRAM. SpaceWire Embedded Core Protocol Handler will be available for the RadHard Eclipse FPGA in the fourth quarter of 2006.
Aeroflex’s RadHard FPGAs are fabricated on 0.25µm five-layer metal ViaLink epitaxial CMOS process. While the part is manufactured on a commercial line, Aeroflex uses proprietary design techniques to increase the products reliability and alleviate single-event effects that typically prevent commercial parts from functioning in a radiation environment. The RadHard FPGAs withstand total dose of 300 krads(Si) tested to MILSTD-883 Method 1019. They are SEL immune to a LET >100MeV-cm2/mg at worst-case voltage and 125°C.
UT6325 RadHard Eclipse FPGA Product
- 0.25µm, five-layer metal, ViaLink(TM) epitaxial CMOS process
- 320,000 usable system gates
- 24 dual-port RadHard SRAM modules
- 208 CQFP, 288 CQPF, 484 CLGA and 484 CCGA packages
- Available to SMD 5962-04229, QML qualified, RadHard to 300krad (Si)
SpaceWire Embedded Core Protocol Handler
- SpaceWire Embedded Core
- Dual ECSS-E-50-12A compliant links
- Data rates from 2 to 100 Mbits/sec
- 9-bit transmit and receive FIFO user interface
- Hard macro for the UT6325 RadHard Eclipse FPGA
- QML Q qualified, RadHard to 300krad (Si)