Category Archives: FPGA

field programmable gate arrays, FPGA design software, PLD, structured ASIC, FPSC, configurable processors

FPGAs For Connectivity Solutions

Learn about heterogeneous network (HetNet) architecture in a Lattice Semiconductor webinar.

Register now for a free webinar on November 21. As the growth in mobile data traffic explodes, learn how the next gen wireless infrastructure is evolving into the heterogeneous network (HetNet) architecture. Lattice Semiconductor will explore the transition from the traditional macro infrastructure to one supplemented with new low power nodes including small cells, low power radios, and millimeter wave backhaul.

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Speeding FPGA Prototype Debug Process with Active Debug and Full Visibility

By Joe Gianelli and Tom Huang

System integration continues to drive the semiconductor design market. This is most obvious when looking at the increased system integration associated with System on Chip (SoC) design over the last few years. Integrating complex hardware features with complex software applications onto one silicon device makes the validation process for today’s SoC designs a tricky one to say the least.

What have been increasingly popular to aid in this complex validation process are FPGA prototype systems. They run extremely fast, almost as fast as the production SoC, and have doubled in capacity every 18 months for the last 5 years. They also enable real world system interfaces to DDRAM, PCI, Ethernet, while using high-speed serial interfaces over 10 Gb/s.

Despite their current strides in speed, capacity, and real world high-speed interfaces, using these FPGA devices to help verify and validate SoC designs are difficult at best due to the many and long FPGA P&R compile times and poor visibility. InPA Systems proposes to address these issues with their active debug and full visibility technology.

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Fast Fourier Transform and FIR Filter Compiler DSP IP Cores

eASIC introduced two new DSP IP cores, an FFT and FIR Filter Compiler. The FT core supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint. The FIR Compiler core (available from Steepest Ascent) can process data streams as high as 500 MSPS and is ideal for Nextreme and Nextreme-2 architectures. The new DSP blocks enable wireless and video/imaging system designers to rquickly migrate costly FPGA-based DSP designs to lower-cost, lower-power Nextreme Series NEW ASICs.

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FPGA and EDA Highlights – 2007.12.21

Webcast: Evaluating Implementation Choices for Low-Power Digital Sound in SOCs
Tensilica has an on-demand webcast entitled, “Evaluating Implementation Choices for Low-Power Digital Sound in SOCs.”

Darnaw1 FPGA Module
Darnaw1 is a Spartan(TM)-3E FPGA module from Enterpoint. The module enables the use of FPGA technology in industrial and military sectors where the volume or assembly technology available precludes the use of BGA packaged FPGA devices. Encapsulating all the elements to support operation of the FPGA, the module has a simple to solder PGA pinout and operates with a single 3.3V power supply.

Nextreme Copper Pillar Bump for Flip Chip Packaging
Nextreme has integrated cooling and power generation into the widely accepted copper pillar bumping process used in high-volume electronic packaging. The innovation in flip chip process technology addresses two of the most serious issues in electronics today – thermal and power management constraints. Nextreme’s approach uses proven, fully scalable technology to deliver new, enabling functionality in flip chip applications.

AKA LCD Controller IP
Advanced Knowledge Associates (AKA) announced that LCD driver core IP is now available as standard on its range of Prepackaged Reconfigurable Integrated System-on-Module (PRISM) solutions. This removes the need for any external controller or device because video displays can be driven directly from the PRISM’s FPGA. It also simplifies the process of integrating LCD and TFT displays into embedded systems.

Embedded Ethernet Applications Market
Ethernet semiconductor vendors will continue to reap benefits from existing fast Ethernet (FE) and gigabit Ethernet (GE) product lines during the 2007-2012 forecast period. However, the more attractive opportunity is the embedded Ethernet applications segment, particularly blade switching and storage networking. With a worldwide CAGR of 6.3% through 2011, this segment will encourage the long-awaited adoption of 10GE technology and provide additional, more robust revenue streams.

Actel IGLOO Icicle Kit
Actel Corporation’ $99 Icicle(TM) Kit enables designers to easily and rapidly program, evaluate, and modify low-power IGLOO-based portable designs. The 1.4″ x 3.6″ Icicle evaluation board, which is powered by a lithium-ion battery, consumes less than one-seventh the power of competitive FPGA development solutions in a design the size of a small cell phone. Actel’s Icicle Kit allows designers to closely examine power consumption in various modes.

Linux in the Embedded Systems Market
According to Venture Development Corporation (VDC), a significant portion of embedded software and systems engineering teams continue to adopt Linux as their primary target operating system. VDC’s research also suggests that this migration may be lasting, as the majority of current Linux users surveyed plan to use Linux again as their primary operating system on future projects.

Aldec Active-HDL 7.3
Aldec, Inc. released Active-HDL 7.3 today. The 7.3 release includes multi-threaded HDL compilation, new waveform viewer, and expanded VHDL 2006 construct support. The new version improves performance in VHDL, Verilog, and mixed RTL compilation and simulation. Active-HDL is a mixed-language design creation, FPGA Project Management and simulation environment supporting VHDL, Verilog, SystemVerilog, and SystemC.

World Markets for Microcontrollers in Automotives
According to Frost & Sullivan, the proliferation of electronic content in automobiles aimed at reducing human errors as well as the growing number of automobile safety features such as additional radars, ultra sonic sensors, cameras, and automatic parking assistance are increasing demaind for microcontrollers. In addition, the introduction of multiplexing in the automotive industry has triggered sales of high performance microcontrollers by amplifying the need for additional processing power and intelligence. According to a Frost & Sullivan report, the automotive microcontroller market generated revenues of $5.83 billion in 2006 and will reach $9.52 billion in 2010.

Pentek Model 7141 Dual Multiband Transceiver
Pentek’s Model 7141 Dual Multiband Transceiver with FPGA is a complete software radio system for connection to HF or IF ports of a communications system and joins Pentek’s family of high-performance PMC/XMC transceiver modules. Model 7141 is an enhanced successor to Pentek’s Model 7140 transceiver, which is widely deployed by many customers for SIGINT, software radio, and communications applications. Pentek has significantly boosted analog performance in the Model 7141 so that the signal-to-noise ratio and the spurious free dynamic range are improved by 10 dB, when compared to many competitive products.

2006-2012 Worldwide Handset Semiconductor Forecast
According to In-Stat, semiconductor components in handsets are the largest semiconductor market in the world by volume, if not in total revenue. In 2007, total revenue from handset semiconductors will exceed $31 billion worldwide.

SANYO CCA-BC200 Automotive Backup Camera System
SANYO Electric Co. selected Altera Corporation’s (NASDAQ: ALTR) Cyclone® II FPGAs and Nios® II embedded processor for the CCA-BC200 Automotive Rear-View Backup Camera System. The Cyclone II FPGA featuring a Nios II embedded processor provides SANYO with a high-performance image-processing solution that minimizes distortion in wide-angle views and hard-to-interpret perspectives. The single-chip FPGA-based approach provides a more compact and reliable solution compared to digital signal processing (DSP) device-based approaches, which typically require two or more devices.

FPGA and EDA News – 2007.12.14

Actel LCD Control Solutions
Actel Corporation announced solutions for liquid crystal display (LCD) control applications. The new IGLOO Video Demo Board, LCD adaptor boards with LCD panels, the IGLOO Video Demo Kit (IVDK), and display-related reference blocks use the 5 microwatt (µW) IGLOO field-programmable gate arrays (FPGAs). The new offerings will be attractive to the power-sensitive designers of portable and handheld consumer, industrial, medical, automotive, and military devices that utilize small-to-medium LCD displays.

Open Source Linux Mobile Computing Platform
ARM ((LSE: ARM); (Nasdaq: ARMHY)) and six companies are teaming together to address the rise in consumer demand for access to the Internet and advanced applications on larger display mobile devices. The collaboration will result in the development of a Linux-based open source platform for next-generation mobile applications. The collaboration builds on the ARM architecture and its ecosystem of Partners to deliver a standards-base platform based on Linux. This group of companies are all working to accelerate the enablement of truly always on, connected mobile computing (CMC) devices.

Lattice LatticeSC/M Supports Quad Data Rate
Lattice Semiconductor Corporation (NASDAQ: LSCC) announced FPGA-based support for Quad Data Rate (QDR) II/II+ memory devices. The LatticeSC(TM) and LatticeSCM(TM) FPGA families (LatticeSC/M) now support QDRII/II+ rates up to 750Mbps. The high-speed QDR II and QDR II+ memory controller IP (intellectual property) is implemented in Lattice’s low power Masked Array for Cost Optimization (MACO(TM)) structured ASIC technology.

A Supercomputer the Size of a Laptop
In a paper (Ultra-compact, low RF power, 10 Gb/s silicon Mach-Zehnder modulator) published in the Optics Express journal, IBM researchers detailed a significant milestone in the quest to send information between multiple cores (“brains”) on a chip using pulses of light through silicon, instead of electrical signals on wires. With this new technology, supercomputers could one day be the size of a laptop. In addition, this laptop supercomputer would expend the energy of just one light bulb.

Precision Synthesis, Xilinx SmartGuide Combo
Precision® Synthesis, from Mentor Graphics Corporation (NASDAQ: MENT), combined with Xilinx® SmartGuide(TM) technology, reduces design time. Test results conducted jointly over the past year using Mentor’s Precision Synthesis tool and the Xilinx SmartGuide functionality show that users saved an average of 40% in mapping and place-and-route (P&R) time. The combined solution preserves unchanged portions of the design when making small changes, reducing overall design iteration time. Tests performed at Xilinx show that over 97% of the components went unchanged and quality of results (QoR) was maintained in the process. These results have also been verified by mutual customers.

PowerQUICC Optimized Java SE for Embedded
Freescale and Sun are optimizing Java SE for Embedded for the PowerQUICC III processor family. The new implementation will enable developers and systems designers may soon incorporate the functionality, security and portability of the Java(TM) SE platform into embedded systems powered by Freescale Semiconductor’s PowerQUICC III processors.

OneSpin Stand-Alone 360 EC-FPGA Equivalence Checker
OneSpin Solutions’ 360 EC-FPGA equivalence checker is now a stand-alone tool. Previously, 360 EC-FPGA was an extension of OneSpin’s 360 EC-ASIC equivalence checker. The stand-alone 360 EC-FPGA equivalence checker is the first sequential equivalence checking solution dedicated to and priced for the FPGA market. 360 EC-FPGA is the only equivalence checker to support all sequential optimizations performed by FPGA synthesis tools. The tool helps designers verify functionality without disabling the advanced synthesis optimizations vital to achieving functional, performance and cost goals.

Microbridge Rejustor Design Challenge
Microbridge is holding a contest — the Rejustor Application Design Challenge. To enter the contest, all you have to do is submit a circuit design idea for any of the rejustor devices available from Microbridge. A rejustor is a polysilicon re-adjustable resistance devices for calibration and temperature compensation.

Altera Zero-Power MAX IIZ CPLDs
Altera Corporation (NASDAQ: ALTR) created the zero-power MAX® IIZ CPLD to address the power, package and price constraints of the portable applications market. Offering a resource advantage of up to six times the density and three times the I/Os compared to competing traditional macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements at the same or lower power while saving board space. MAX IIZ devices deliver the many benefits of CPLDs—including flexibility, faster time to market, and board-level integration—to handsets and other portable applications. Altera optimized MAX IIZ devices to offer the best combination of zero power, small package,and low cost.

Screencast: Driving a Robot from Windows Mobile with Microsoft Robotics Studio
Check out Olivier Bloch’s webcast on using Microsoft Robotics Studio to build a service that runs on a Windows Mobile phone. The screencast shows how to use Robotics Studio to remotely drive a robot (connected via Bluetooth) from a Windows Mobile device.

Tensilica TRAX-PC Processor Trace
Tensilica®, Inc. added an optional full-speed, non-intrusive instruction trace capability to its configurable processor cores. Tensilica’s TRAX-PC processor trace capture macrocell is Nexus 5001 compatible and ideal for debugging complex, challenging real-time applications such as engine and motor control. Software control and use of the on-chip TRAX hardware is fully integrated into Tensilica’s Xplorer(TM) integrated design environment (IDE) so software engineers can easily develop and debug programs while using the TRAX-PC trace macrocell.

Discrete Power Semiconductors Grow in Automotive Market
According to Frost & Sullivan, discrete power semiconductors and microcontrollers will find significant opportunities in automotives as hybrid and electric vehicles gain popularity. End-user market expansion, increased automobile multiplexing, and wider application of vehicle integrated circuits (ICs) will likely sustain their growth. In their report, World Markets for Discrete Power Semiconductors in Automobiles, Frost & Sullivan indicates that the market generated revenues of $1.76 billion in 2006 and will reach $2.66 billion in 2010.

Altera Stratix III FPGA Features 1067 Mbps DDR3 Speed
Altera Corporation (NASDAQ: ALTR) Stratix® III FPGAs has achieved DDR3 memory interface speeds in excess of 1067 Mbps. The result is a 33% advantage in memory performance over competing FPGA solutions. The higher memory bandwidth enables new communications, computing, and video processing applications that were either previously impossible or required doubling the number of memory banks. Altera’s Stratix III FPGA family is the industry’s only FPGA to demonstrate full compliance to the JESD79-3 JEDEC DDR3 SDRAM standard, including the performance-critical read/write-leveling specification for maximum system performance.

VPN Firewall Upgrade System Patent
O2Micro® International Limited (NASDAQ:OIIM) (SEHK:0457) was issued 17 claims under Great Britain (GB) patent number 2,425,627 for its Field Programmable Gate Array (FPGA) IC upgrade system in VPN Firewall solutions.

FPGA and EDA Highlights – 2007.12.07

Seminar: Accelerating Silicon Success with Silicon Aware IP
Virage Logic Corporation (NASDAQ:VIRL) and TSMC are offering a free technical lunchinar and demonstration entitled, Accelerating Silicon Success with Silicon Aware IP for Yield Acceleration & Time-to-Volume. The seminar and demonstration will focus on bridging the gap between design and manufacturing and will highlight the STAR(TM) Memory System with the new STAR(TM) Yield Accelerator option for advanced design and process technology challenges. The event will take place on December 11, 2007.

Xilinx SPI-4.2 and SFI-4.1 Solutions
Xilinx Inc. (Nasdaq: XLNX) has developed solutions for the Optical Internetworking Forum (OIF) System Packet Interface (SPI) 4.2 and SerDes Framer Interface (SFI) 4.1 standards, the industry’s highest performance channelized packet interfaces. Xilinx’s solutions are based on Virtex(TM)-5 LXT FPGAs and feature the ML550 hardware verification board, SPI-4.2 LogiCORE(TM) IP, and SFI-4.1 reference design. Verified across multiple FPGA platforms, the solutions accelerate the design cycle of wired networking systems that require OC-192 (10 Gbps), multiple OC-48 (2.5 Gbps) or 10 Gbps Ethernet interfaces, resulting in much faster time-to-market than competing solutions.

SEMI October 2007 Book-to-Bill Ratio
According to Semi, North American manufacturers of semiconductor equipment posted $1.23 billion in orders in October 2007 (three-month average basis) and a book-to-bill ratio of 0.83. A book-to-bill of 0.83 means that $83 worth of orders were received for every $100 of product billed for the month.

Xilinx SpeedWay Workshops
Avnet Electronics Marketing announced a new series of SpeedWay Design Workshops(TM) featuring Xilinx® technology. The workshops are available in locations across the U.S. through March 2008.

IPextreme World 2007
IPextreme recently announced their annual intellectual property (IP) conference. The event will take place Tuesday, December 11, 2007 at the Ambassador Hotel in Hsinchu, Taiwan. This year’s show is titled “IP Fuels the Semiconductor Industry.” The conference will feature semiconductor IP presentations from IPextreme, Freescale, Infineon, NXP Semiconductor, and Texas Instruments. In addition, ChipEstimate will demonstrate their software for planning chips with high IP content.

Webinar: How to Quickly Design a Low-Cost ASIC
NEC and Tensilica are sponsoring a webinar on how to quickly design low-cost custom logic. The webcast will take place on Thursday, December 6th at 11 am Pacific (2:00 pm Eastern). The seminar will focus on designing low-cost ASICs using synthesizable 200-megahertz (MHz) 32-bit controllers.

Selecting the Right Isolation Solution Webcast
Texas Instruments Incorporated (TI) (NYSE: TXN) and Arrow Electronics Inc. is offering a live Analog eLab(TM) Webcast. The event will take place Wednesday, December 12, 2007, at 11:00 a.m. CST (18:00 hrs CET). The webinar is titled “Selecting the Right Isolation Solution.”

IEEE 1588 Clock Synchronization for Lattice FPGA
Today Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the availability of Industrial Ethernet Intellectual Property (IP) from Oregano Systems Design and Consulting. Oregano ported their IEEE 1588 IP core for clock synchronization over Ethernet to the LatticeXP(TM) and LatticeXP2(TM) FPGA families. Oregano’s IP core implements a popular IEEE standard that is used for many Industrial Ethernet applications to ensure that the various nodes in a network have synchronized real time clocks. The solution can be delivered as a standard IP core or Oregano can program it onto a LatticeXP or LatticeXP2 device and deliver it as an Application Specific Standard Product (ASSP).

Q3 2007 Semiconductors Equipment Market
SEMI recently reported that worldwide semiconductor manufacturing equipment billings reached $11.13 billion in the third quarter of 2007. The billings figure is one percent greater than the second quarter of 2007 and about one percent greater than the same quarter a year ago. The data is gathered from more than 150 global equipment companies that provide data on a monthly basis.

Microtronix ViClaro III Video IP Development Kit
Microtronix, with the help of Altera, recently developed the ViClaro III HD Panel Display Interface – Video IP Development Kit. The ViClaro III kit helps high-definition (HD) video display designers build highly integrated, next-generation HD 1080p, 100-/120-Hz frame rate conversion television sets or panel display systems. The ViClaro III kit, which uses the Cyclone III FPGA as its engine, provides a comprehensive engineering design and evaluation platform. With the kit, designers can efficiently develop video-processing IP algorithms to support an array of display applications providing superior picture quality.

Android Developer Challenge
In case you missed it, Google recently announced the Android Developer Challenge. The contest will provide $10 million in prizes for building mobile applications on the Android platform. The Challenge will award cash prizes (ranging from $25,000 to $275,000) to developers whose applications are picked by a panel of judges.

Programmable Solutions India 2007
Xilinx, Inc. (Nasdaq: XLNX) and CG-CoreEl will host Programmable Solutions India 2007 on December 11, 2007 in Bangalore and December 13, 2007 in Hyderabad. The events offer a full-day, complimentary line-up of keynotes, presentations, demonstrations and solution centre exhibits at each location to showcase industry-leading programmable solutions. Attendees will learn about silicon, IP, software, solutions and services from Xilinx and its network of solution providers, including Avnet, Nu Horizons, Agilent Technologies, Mentor Graphics, Wind River, iWave, Synplicity, and Nital.

TED Virtex-5 LX Multi-Application Evaluation Platform

Tokyo Electron Device (TED) has developed a multi-application evaluation platform for the Xilinx(R) Virtex-5 LX 330 FPGA family. TED’s Virtex-5 LX Multi-Application Evaluation Platform enables efficient design and evaluation of a wide range of high-speed applications, including consumer products such as high definition televisions, set-top boxes and printers, as well as telecommunications equipment, medical devices and miscellaneous industrial equipment.

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Lattice DDR2 SDRAM Controller IP Core

Lattice’s (NASDAQ: LSCC) 533 Mbps DDR2 SDRAM IP core is optimized for the LatticeECP2(TM) and LatticeECP2M(TM) low-cost FPGA families, as well as its high-end LatticeSC(TM) Extreme Performance(TM) FPGA family.

The Double Data Rate Synchronous Dynamic Random Access Memory Controller IP core interfaces seamlessly with industry standard DDR2 SDRAM memory devices and has been performance-tuned for Lattice FPGAs. Not only does this IP core support all DDR2 commands, it also is extremely flexible, with intelligent bank management to minimize active commands, a synchronous implementation for reliable operation and a command pipeline to maximize throughput. The most common memory configurations are supported through a combination of variable address widths for different memory devices, programmable timing parameters, byte level writing through data mask signals and burst termination.

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Xilinx Spartan-3AN FPGA

The Spartan(TM)-3AN FPGA platform, by Xilinx (NASDAQ: XLNX), combines the performance and functionality advantages of SRAM-based technology with reliable non-volatile flash technology in a single-chip solution. With the industry’s largest user flash memory and enhanced security capabilities, this new platform is optimized specifically for non-volatile applications where higher system integration or security is critical. With up to 1,000X more on-chip user flash as compared to its nearest competitor, the Spartan-3AN platform offers unprecedented system flexibility, significantly outperforming competing non-volatile FPGAs.

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