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'FPGA' Category Archive

Speeding FPGA Prototype Debug Process with Active Debug and Full Visibility

Posted by Ken Cheung in Articles,FPGA,Test Solution on Monday, August 16, 2010

By Joe Gianelli and Tom Huang Introduction System integration continues to drive the semiconductor design market. This is most obvious when looking at the increased system integration associated with System on Chip (SoC) design over the last few years. Integrating complex hardware features with complex software applications onto one silicon device makes the validation process [...]

Fast Fourier Transform and FIR Filter Compiler DSP IP Cores

Posted by Ken Cheung in DSP,FPGA,IP Core on Wednesday, May 6, 2009

eASIC introduced two new DSP IP cores, an FFT and FIR Filter Compiler. The FT core supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint. The FIR Compiler core (available from Steepest Ascent) can process data streams as high as 500 MSPS and is ideal [...]

FPGA and EDA Highlights – 2007.12.21

Posted by Ken Cheung in FPGA on Friday, December 21, 2007

Webcast: Evaluating Implementation Choices for Low-Power Digital Sound in SOCs Tensilica has an on-demand webcast entitled, “Evaluating Implementation Choices for Low-Power Digital Sound in SOCs.” Darnaw1 FPGA Module Darnaw1 is a Spartan(TM)-3E FPGA module from Enterpoint. The module enables the use of FPGA technology in industrial and military sectors where the volume or assembly technology [...]

FPGA and EDA News – 2007.12.14

Posted by Ken Cheung in FPGA on Friday, December 14, 2007

Actel LCD Control Solutions Actel Corporation announced solutions for liquid crystal display (LCD) control applications. The new IGLOO Video Demo Board, LCD adaptor boards with LCD panels, the IGLOO Video Demo Kit (IVDK), and display-related reference blocks use the 5 microwatt (µW) IGLOO field-programmable gate arrays (FPGAs). The new offerings will be attractive to the [...]

FPGA and EDA Highlights – 2007.12.07

Posted by Ken Cheung in FPGA on Friday, December 7, 2007

Seminar: Accelerating Silicon Success with Silicon Aware IP Virage Logic Corporation (NASDAQ:VIRL) and TSMC are offering a free technical lunchinar and demonstration entitled, Accelerating Silicon Success with Silicon Aware IP for Yield Acceleration & Time-to-Volume. The seminar and demonstration will focus on bridging the gap between design and manufacturing and will highlight the STAR(TM) Memory [...]

TED Virtex-5 LX Multi-Application Evaluation Platform

Posted by Ken Cheung in EDA Tools,FPGA on Monday, August 20, 2007

Tokyo Electron Device (TED) has developed a multi-application evaluation platform for the Xilinx(R) Virtex-5 LX 330 FPGA family. TED’s Virtex-5 LX Multi-Application Evaluation Platform enables efficient design and evaluation of a wide range of high-speed applications, including consumer products such as high definition televisions, set-top boxes and printers, as well as telecommunications equipment, medical devices [...]

Lattice DDR2 SDRAM Controller IP Core

Posted by Ken Cheung in FPGA,IP Core on Wednesday, August 15, 2007

Lattice’s (NASDAQ: LSCC) 533 Mbps DDR2 SDRAM IP core is optimized for the LatticeECP2(TM) and LatticeECP2M(TM) low-cost FPGA families, as well as its high-end LatticeSC(TM) Extreme Performance(TM) FPGA family. The Double Data Rate Synchronous Dynamic Random Access Memory Controller IP core interfaces seamlessly with industry standard DDR2 SDRAM memory devices and has been performance-tuned for [...]

Xilinx Spartan-3AN FPGA

Posted by Ken Cheung in FPGA on Tuesday, June 26, 2007

The Spartan(TM)-3AN FPGA platform, by Xilinx (NASDAQ: XLNX), combines the performance and functionality advantages of SRAM-based technology with reliable non-volatile flash technology in a single-chip solution. With the industry’s largest user flash memory and enhanced security capabilities, this new platform is optimized specifically for non-volatile applications where higher system integration or security is critical. With [...]

Altera Automotive Graphics System

Posted by Ken Cheung in FPGA on Tuesday, May 29, 2007

The Altera(R) Automotive Graphics System (AAGS) is a scalable solution that enables design engineers to quickly and efficiently design multiple automotive infotainment products based on a single electronic design. Implemented in Altera’s low-cost Cyclone(R) series or high-performance Stratix(R) series FPGAs, the AAGS enables designers to overcome the lengthy and costly design cycles of fixed-function graphic [...]

Xilinx Virtex-4 QPRO FPGAs for Aerospace and Defense

Posted by Ken Cheung in FPGA on Wednesday, May 16, 2007

Xilinx Virtex-4 QPRO MIL-grade FPGAs are designed for the aerospace and defense industry. The Virtex-4 QPRO FPGAs provides the industry’s most comprehensive ‘space to base’ device portfolio with higher performance, lower power options, and full military temperature-qualification. The new Virtex-4 QPRO family builds on the existing Virtex-II QPRO device offering, which includes the industry’s first [...]

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