LVDS receiver from Texas Instruments supports a 4 MHz pixel clock, reduces power consumption

Texas Instruments has announced the new SN65LVDS822 FlatLink Low-Voltage Differential Signaling (LVDS) receiver IC that supports a 4 MHz pixel clock in appliances, digital cameras, copiers, fuel pump displays, or printers with small LCD screen panels.

The receiver accepts a lower pixel clock, which allows the SN65LVDS822 a 30 percent longer video transmission distance, and 60 percent fewer wires to reduce power consumption as well as Electromagnetic Interference (EMI).

Key features of the SN65LVDS822:

  • Supports wide pixel clock range: Supports 4 MHz to 54 MHz to enable panel resolutions of 160 by 120 (QQVGA) to 1024 by 600 (WUXGA) at 60 frames per second (fps) with 24 bit-per-pixel (bpp) color.
  • Reduced wire count: Supports both 4:27 and 2:27 deserialization, providing the flexibility to further reduce wire count. The 2:27 mode with 14x sampling enables a 40 percent lane count reduction to two data lanes for systems with tight space constraints.
  • Flexible PCB layout and low EMI: Bus swap feature and reduced LVDS swing offer engineers greater board design flexibility, while the 3-way selectable CMOS slew rate control reduces EMI by matching the slew rate with the needs of the application.
  • LVCMOS output: Supports 1.8-V to 3.3-V CMOS signals to meet a wide range of LCD panel requirements.

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