Ambarella A7 IP Camera SoC for Video Surveillance

Ambarella introduced the A7 IP Camera SoC for video surveillance applications. The Ambarella A7 features an ARM CPU, multi-streaming 1080p60 H.264 encoder, up to 500 MHz pixel capture rate (equivalent to 8 Megapixels at 60 frames per second), and power consumption of less than 1.5 Watts. The chip’s 3D motion compensated noise reduction eliminates the motion smearing and ghosting artifacts that are commonly associated with motion adaptive 3D filtering. The Ambarella A7 IP Camera SoC is sampling now.

Ambarella A7 IP Camera SoC for video surveillance applications

Ambarella A7 IP Camera SoC Features

  • 12-lane SLVDS, HiSPI and parallel interface
  • 500 MHz pixel capture rate, 32 MPixel sensor support
  • BT.601/656/1120 YUV video in
  • Dual digital video out; HDMI, BT.656/1120, RGB
  • Composite video out
  • Lens shading and chromatic aberration correction
  • Black level correction
  • Barrel compensation
  • Defect pixel cluster correction
  • CFA crosstalk and fixed pattern noise filtering
  • RGB Bayer demosaicing
  • 3D color transformation with gamma
  • 3D motion-compensated noise reduction (MCTF)
  • Digital WDR contrast enhancement
  • AE/AWB/AF libraries supplied
  • Day/Night and DC/Stepper iris control
  • Flicker suppression
  • Four independent resizers with digital PTZ
  • Crop, mirror, flip, 90 degree rotation
  • Alpha-blending OSD; text, overlays, privacy mask
  • Video warp engine
  • 1.5 W power consumption for 1080p60 encode
  • H.264 BP/MP/HP Level 5.1, up to 1080p60+VGA
  • Encode of 4MP@30fps, 5MP@24fps, 10MP@10fps
  • MJPEG – over 200 Mpixels/s
  • Up to 32 Megapixel encode resolution
  • Broadcast-grade ME; up to 1920 pel search range
  • Dynamic GOP, intra refresh, IDR insertion
  • Sub-frame low-delay encoding
  • CABAC up to 50 Mbps, CAVLC up to 100 Mbps
  • Multi-streaming with on-the-fly changes of frame rate, bit rate, resolution, and GOP
  • CBR, VBR, and Capped VBR with quality/fps priority
  • 555 MHz ARM1136J-S CPU
  • AES/3DES/SHA-1/MD-5 hardware crypto engine
  • 32-bit DDR2/LPDDR2/DDR3, 372 MHz
  • SMIO controller for NAND, SDIO (2), CF, MMC, IDE
  • Dual Ethernet MII and USB 2.0 Device
  • I2S (6), SSI/SPI (3), IDC (3), PWM (5), RS-232C/485 (2)
  • GPIO (up to 155), Stepper motor (4 sets), ADC (6 ch)
  • Host interface (Intel/Motorola), RTC, WDT, JTAG
  • 15×15 mm, 528 ball FPGA package
  • Operating temperature: -20¢°C to +85¢°C

More information: Ambarella