MIPS32 1074K Coherent Processing System

MIPS Technologies announced the MIPS32 1074K Coherent Processing System (CPS). The new processor is a fully-synthesizable multicore IP that approaches production frequencies of 1.5 GHz in 40nm G process. The MIPS 1074K CPS will be available in October 2010. Two initial versions of the 1074K CPS will be available: the MIPS32 1074Kc CPS, which provides a coherent processing system using base integer cores, and the MIPS32 1074Kf CPS, which includes a floating point unit (FPU) in each core.

MIPS Technologies MIPS32 1074K Coherent Processing System (CPS)

MIPS32 1074Kf CPS Features

  • 1 to 4 1074K “base” cores (1074K base core = 74K superscalar, out-of-order high-performance processor with 15-stage pipeline, and cache coherence structures)
  • Coherence Management (CM) unit – high throughput coherence fabric supporting 256-bit wide buses internally on key datapaths, as well as external read and write data interfaces to L2 cash and through to rest of system logic in SoC implementation
  • I/O Coherence Unit (IOCU) – hardware acceleration for I/O coherence, offloading software implementation on CPUs
  • Cluster Power Controller (CPC) – multicore power gating, clock gating, and reset management
  • Global Interrupt Controller (GIC) – system and inter-processor interrupt controller
  • EJTAG/PDtrace block for advanced debug/trace of complete coherent system
  • MIPS 32 1074Kf core version has IEEE 754-compliant FPU per core, compliant to MIPS 64-bit FPU architecture
  • Supports single- and double-precision data types
  • Separate in-order, dual-issue pipeline decoupled from integer pipeline in each core
  • Manages coherency using the MESI protocol
  • Global Configuration Registers (GCRs) for configuring/controlling CM scheme
  • Provides highly scalable performance/power management via shutdown and bring up of one or more cores in the coherent processing system via clock or voltage island control
  • Works in conjunction with each core implemented in a separate power domain
  • Bridges non-coherent I/O peripheral transfer and makes transactions coherent
  • Supports per-transaction attributes for snooping L1 caches, L1+L2 caches, or non-coherent transactions, plus I/O prioritization
  • Supports system-level interrupts; inter-processor interrupts
  • Routes interrupts to a particular core or VPE
  • Configurable number of system interrupts (up to 256)

More information: MIPS Technologies