Novelics introduced the coolSRAM-6T embedded memory IP and MemQuest compiler, which are enhanced with Novelics 3G optimizations. The coolSRAM-6T IP is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs. The coolSRAM-6T enables ASSP and ASIC designers to achieve higher performance and more power-efficient system-on-chips (SoCs). The SRAM-6T in 40nm is available for licensing now. The initial offering is offered in TSMC’s 40nm GP / LP technologies. Support for UMC, GF, and SMIC will also be offered.
Novelics MemQuest compiler environment enables architectural analysis for access time, active power, leakage, and area. coolSRAM-6T IP includes an embedded grid-style power mesh. The power supply lines are available for user tapping, which are located on Metal 4 for best power integrity and simplest IR-drop analysis. This arrangement can support up to a 512 bit-wide bus to achieve great bandwidth and g up to 2 Mbits of block size.
The coolSRAM-6T IP enables the use of standard Vt (SVT) transistors or High Vt (HVT) transistors to achieve the best tradeoffs between speed and leakage. For further reduction of leakage, Novelics’s source biasing technique is available. This is complemented with advanced power gating techniques. Three easy to use power modes are offered: These are (1) a low leakage active mode when an operation is performed, (2) a lower leakage standby mode where data is retained but no operations can be performed, and (3) a sleep mode where leakage is minimized and data is destroyed.
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