Signatec introduced the PX1500-4 high-speed digitizer. The PX1500-4 captures four synchronized channels at sampling rates up to 1.5 GHz, or two synchronized channels up to an amazing 3 GHz when interleaving the ADC data. Dual embedded Virtex-5 FPGAs control the PX1500-4 board functionality with available DSP Slice and logic resources optionally available in both chips for custom in-line signal processing. Signatec’s PX1500-4 is currently shipping with a 6 week delivery forecast.
The Signatec’s PX1500-4 features 2 GB of on-board memory configured as a large FIFO and a PCIe x8 bus. It can continuously sustain long recordings at up to 1.4 GB/s through the PCIe x8 bus (both mechanical and electrical) to PC disk storage without any break in the analog record.
The PX1500-4′s frequency synthesized clock allows the ADC sampling rate to be set to virtually any value from 200 MHz, the minimum allowable ADC clock, up to 1500 MHz, offering maximum flexibility for sampling rate selection. Additional divide-by-2 circuits are provided for sampling at even lower frequencies. This frequency selection flexibility comes at no cost to the acquisition clock quality/performance when locked to either the onboard 10 MHz, 5 PPM reference clock or to an externally provided 10 MHz reference clock. The ADC may also be clocked from an external clock source.
This level of accurate clock tuning without sacrificing performance gives the best integrated onboard ADC clock flexibility in the industry. Users no longer need to settle for fixed clocks or limiting divide-by-2 clocks only. This feature is ideal for undersampling applications, where the Nyquist bands need to be perfectly tuned to optimally place the center frequency of the sampled signal into the middle of the Nyquist zone and to optimize for the total bandwidth or data captured. In addition to the onboard clock capabilities, the ADC may also be clocked from an external clock source.
Up to three PX1500-4 boards may be interconnected in a Master/Slave configuration via a ribbon cable that connects at the top of the board. In this configuration the clock and trigger signals from the Master drive the Slave boards so that data sampling on all boards occurs simultaneously. Up to six boards can be set up for fully synchronized operation by utilizing the SYNC1500-6 as the clock and trigger source for the system, where all six boards can function synchronously even when placed into different PC chassis. This scalability of chassis and system resources allows for increasing the sustained data rate per channel for high speed signal recording and/or real-time processing applications.
In Segmented Mode, ‘time stamps’ allow for storing the time relationship between the memory segments. Time Stamps are 64 bit timer values with a clock resolution of 4/fADC, and are accumulated in a 2048 element FIFO memory separate from the data. If necessary, time stamps may be read during acquisition in order to prevent overflow. This is possible in any acquisition mode.
More info: Signatec