Sundance announced the EVP6472 embedded development platform. The EVP6472 off-the-shelf multiprocessor, multicore solution features dual Texas Instruments (TI) TMS320C6472 Digital Signal Processors (DSPs). The EVP6472 offers design support from 3L’s Diamond multiprocessor tool-suite. Diamond enables easy access to the on-board 12 C64x+ cores and allows the designer to rapidly build, model, test, and iterate different design architectures by moving tasks between the processor cores. The EVP6472 is available for order with shipping in December 2009. Prices start at $2000.00 for a limited time.
The EVP6472 embedded development platform includes a TIM carrier card and a modular plug-in that features a dual C6472 multicore DSP, a Virtex5 FX30 FPGA with embedded PowerPC, 2 banks of DDR2 memory, Rocket Serial Link (RSL) connectors, and a host USB 2.0 interface. The development platform is supported by TI’s Code Composer Studio (CCS), and the 3L Diamond tool-suite that enables developers to separate the implementation of their application into: a software section based around communicating tasks; and, a hardware section built from processors joined by data-transfer links. Tasks can be placed on any of the twelve C64+ cores and the Diamond API allows the efficient exchange of data between tasks. Diamond uses its built-in device drivers to support uniform communication, automatically using the shared memory between tasks and a virtual channel system is also available for deadlock-free data routing.
The EVP6472 is ideal for the development of high-performance applications (such as high-end industrial, mission critical, test and measurement, communication, medical imaging, blade server, and high-end image and video processing).
The six-core TI C6472 DSP leads the industry in power consumption efficiency. The 500MHz C6472 is the best power performance multicore DSP with 0.15 mW/MIPS at 3 GHz performance. The 700MHz C6472 with a total 4.2 GHz performance and 4.8 MB on-chip L1/L2 memory is among the highest performance DSPs from TI. The C6472 architecture was designed to ensure a maximized subsystem performance on a chip. One of the advantages of this architecture is that in addition to dedicated Layer 1 (L1) and Layer 2 (L2) memory to each core, C6472 features 768KB shared L2 program/data memory and a shared memory controller to facilitate high efficient and flexible inter-DSP core communications.