MIPS M14K Microcontroller Core Family

MIPS Technologies launched the M14K core family for extremely cost-sensitive embedded applications. The MIPS32 M14K and M14Kc cores are the first MIPS32 compatible cores that also execute the new microMIPS instruction set architecture (ISA), achieving high performance of 1.5 DMIPS/MHz with an advanced level of code compression. The microMIPS ISA maintains 98% of MIPS32 performance while reducing code size by 35%, translating to significant silicon cost savings. The M14K cores are ideal for 32-bit microcontrollers (MCUs), home entertainment, personal entertainment, and home networking. The new M14K and M14Kc cores will be available in the first quarter of 2010.

The M14K core combines high performance with an advanced level of code compression for the 32-bit MCU market, achieving performance of 1.5 DMIPS/MHz and 180 MHz in 130nm. The M14K core offers advanced features that are optimized for MCU and real-time embedded applications, including reduced interrupt latency, flash acceleration, advanced debug features including iFlowTrace and support for AHB Lite as the interconnect interface. Designed on the MIPS32 4K micro-architecture that is already proven in hundreds of millions of SoCs, the M14K core is highly configurable and extendable, offering a wide range of implementation options to minimize cost and maximize reusability.

The M14Kc core builds on the base M14K core with additional features for embedded applications such as home entertainment, home networking and personal mobile entertainment. These applications require a compact footprint but also the ability to execute increasingly complex software algorithms on an RTOS or Linux. Based on the popular MIPS32 4KEc micro-architecture, which provides a powerful Linux and Java engine and superior performance for the Android platform, the M14Kc core has a full cache controller and translation lookaside buffer (TLB) memory management unit (MMU).

At the heart of the M14K and M14Kc cores is the new microMIPS ISA that offers 32-bit performance with 16-bit code size for most instructions. The microMIPS ISA combines recoded and new 16- and 32-bit instructions to achieve an ideal balance of performance and code density. It incorporates all MIPS32 instructions and Application Specific Extensions (ASEs) including MIPS-3D ASE, MIPS DSP ASE, MIPS MT ASE and SmartMIPS ASE, as well as new instructions for advanced code size reduction. The microMIPS ISA is backward compatible, enabling reuse of optimized MIPS micro-architecture. With smaller memory accesses and efficient use of the instruction cache, the microMIPS ISA also helps to reduce system power consumption.

More info: MIPS Microcontrollers