ADRES Processor Architecture for Dynamically Reconfigurable Embedded Systems

IMEC announced the second generation of their ADRES processor architecture (architecture for dynamically reconfigurable embedded systems). ADRES now supports multithreading, and has doubled its performance and energy efficiency compared to the first ADRES generation. This positions ADRES as a building block for future 4G devices. ADRES can be licensed from IMEC and is targeted at chip manufacturers. Companies interested in further developing this technology are welcome to join in IMEC’s collaborative research.

ADRES is a processor architecture designed for wireless and multimedia processing in single- and multiprocessor systems. ADRES processors are suited for future mobile terminals, such as software-defined radios. They combine state-of-the-art power efficiency, excellent performance, and flexibility. Through an XML template, designers can create the ADRES processor instance that is best suited for their applications. Applications for an ADRES processor can be completely programmed in a high-level programming language (C) and compiled with IMEC’s DRESC compiler. This is of key importance for a short time-to-market.

The current architecture is designed to support 600Mbps 802.11.n on two cores with a total power use of 220mW, using 40nm technology. Compared to the first generation ADRES, this is a doubling of both performance and energy efficiency. In addition, ADRES will be extended with wide SIMD in 2010. This will improve the energy efficiency by another 30%.

IMEC’s second generation ADRES is a stepping stone for its research into a baseband processor that will support the full 4G requirements. These include wireless connectivity up to gigbits/s, runtime resource management, support for 4×4 MIMO, and support for the latest versions of the WiFi and LTE standards.

More info: IMEC