ARM Cortex-A9 MPCore Hard Macro Implementations

ARM developed two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process. The hard macro implementations enable silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz. The Cortex-A9 hard macros and the corresponding optimized physical IP used to develop the speed-optimized and power-optimized implementations are available for license today with delivery in the fourth quarter of 2009.

The Cortex-A9 speed-optimized hard macro implementation will provide system designers with an industry standard ARM processor incorporating aggressive low-power techniques to further extend ARM’s performance leadership into high-margin consumer and enterprise devices within the power envelope necessary for compact, high-density and thermally constrained environments. The hard macro implementation operates in excess of 2GHz when selected from typical silicon and represents an ideal solution for high-margin performance-oriented applications.

The Cortex-A9 power-optimized hard macro implementation delivers its peak performance of 4000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon. The implementations are ideal for thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer and high-density enterprise applications, energy efficiency is of paramount importance.

The hard macro implementations include ARM AMBA-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area. Each Cortex-A9 hard macro implementation also includes the CoreSight Program Trace Macrocell (PTM) which provides full visibility into the processor’s instruction flow, enabling the software community to develop code for optimal performance.

Both ARM dual core Cortex-A9 hard macros will share a common seven-power domain, dual-NEON technology configuration supporting SMP (symmetrical multiprocessing) operating systems with up to 8MB of Level2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.

More info: ARM