Tensilica ConnX D2 DSP Engine

Tensilica announced the ConnX D2 16-bit dual-MAC (Multiply Accumulator) DSP (Digital Signal Processor) engine for the Xtensa LX dataplane processor cores. The ConnX D2 DSP engine delivers high performance from C code. As a result, virtually any C program, including those written with C intrinsic functions for the TI C6x family or ITU (International Telecommunications Union) reference code, can run unmodified and with excellent performance on the ConnX D2 DSP engine. The ConnX D2 DSP option for the Xtensa LX processor will be available in October 2009.

Tensilica ConnX D2 Dual-MAC, 16-bit Fixed-Point Communications DSP Engine

ConnX D2 Features and Benefits

  • Both SIMD and 2-way FLIX (parallel VLIW) operations
  • Optimized, vectorizing XCC Compiler
  • High-performance DSP instruction set
  • Dual write ports compute up to three results/cycle
  • Supports TI (C6x) and ITU-T C intrinsic code base
  • Bit-for-bit compatible with TI C6X code
  • C-centric programming model supports standard C 16-bit, 32-bit and 40-bit data types
  • Outstanding “out of the box” performance on compiled C source
  • Reduces or eliminates the need for assembly code
  • Performance acceleration for vectorizable code
  • VLIW parallel execution for non-vectorizable code
  • Large base of pre-optimized C code
  • Quick and easy compiling of C code optimized with TI C6x intrinsics
  • Quickly leverage all ITU-T reference code using ITU C intrinsics

Because of its large ITU software code base available, the customizable ConnX D2 DSP engine is ideal for telecom infrastructure and VoIP (Voice over Internet Protocol) applications. In addition, its small size (less than 70,000 gates) makes the ConnX D2 DSP engine is ideal for a wide variety of low-power portable consumer applications including mobile wireless devices, next-generation disk drives and data storage, home entertainment devices, and computer peripherals.

The ConnX D2 DSP engine supports a wide range of data types (e.g., 16-, 32-, and 40-bit integer and fixed point; 16-bit complex; 8- and 16-bit vector), seven addressing schemes, and data manipulation instructions including shifting, swapping, and logical operations to provide outstanding performance on DSP algorithms. For specific DSP algorithm acceleration, the ConnX D2 engine instructions include Add-Compare-Exchange (used with Viterbi), Add Modulo, Add Subtract, and Add Bit Reverse Base. Used in conjunction with a bit reversed addressing scheme, this instruction set delivers extremely efficient FFT implementations.

The ConnX D2 SIMD unit is supported by a comprehensive set of instructions for vector loads and stores that support multiple data widths and SIMD data register loading orders, which can be aligned or unaligned.

Every Xtensa LX DPU with (or without) the ConnX D2 DSP engine is automatically generated with a complete set of software development and modeling tools matched to the exact DPU configuration. Designers use Tensilica’s Xtensa Xplorer Eclipse-based GUI (graphical user interface) as the cockpit for the entire design experience. From Xtensa Xplorer, designers can profile their application code and make the changes in the processor necessary to speed up that code. Designers can also pick from options for processor interfaces, memories, operating systems support, EDA scripts, debug and trace, and more.

More information: Tensilica ConnX D2 DSP Engine (pdf)