Fast Fourier Transform and FIR Filter Compiler DSP IP Cores
eASIC introduced two new DSP IP cores, an FFT and FIR Filter Compiler. The FT core supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint. The FIR Compiler core (available from Steepest Ascent) can process data streams as high as 500 MSPS and is ideal for Nextreme and Nextreme-2 architectures. The new DSP blocks enable wireless and video/imaging system designers to rquickly migrate costly FPGA-based DSP designs to lower-cost, lower-power Nextreme Series NEW ASICs.
eASIC Fast Fourier Transform (FFT) Features
- Performance up to the 300 MHz max in Nextreme-II Devices
- Performance up to the 190 MHz max in Nextreme Devices
- Maximum Throughput of 90 MSPS in Nextreme-II and 54 MSPS in Nextreme
- Transform sizes from 8 to 16K points with the option to be run-time programmable
- Two architectural implementation options providing the most area efficient implementation for a given data rate
- A fixed point bit-accurate C-Model to enable system level analysis of eASIC FFT core
- Drop in replacement for FPGA FFT IP to simplify cost and power reduction transition to eASIC
- Bit width trade off (8-18 bits) enable a resource efficient implementation given the algorithmic constraints
- Run-time configurable forward or inverse operation and scaling schedule
- RTL Verilog Code keeps design transparent and open to the user
Steepest High-Speed FIR Filter Compiler Features
- Generates single-rate and multi-rate (interpolation / decimation) filters
- Single-channel or multi-channel operation, applicable to both single-rate and multi-rate operation
- Multi-rate filters are implemented using polyphase decomposition techniques
- Highly optimized multiplier block synthesis
- Automatic optimization of symmetric and halfband filter types
- Filter designs provided in VHDL
- Realizes user specified filters with very low hardware cost
- Fully pipelined implementation yields very high clock rates and sampling rates
- Full-precision word length at all arithmetic stages through to the output
- Supports signed or unsigned input samples and signed or unsigned coefficients with configurable word lengths
More information: eASIC | Steepest Ascent
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.