BSQUARE Announces Embedded CE 6.0 BSP for TI Cortex-A8 OMAP35x EVM
BSQUARE Corporation (Nasdaq: BSQR) announced the availability of a Windows Embedded CE 6.0 board support package (BSP) for the Cortex[tm]-A8 processor-based OMAP35x evaluation module (EVM) from Texas Instruments Incorporated (TI) (NYSE: TXN). Developers of industrial, automotive and consumer applications now have access to a free source code offering for Windows Embedded CE operating system-based designs to get their OMAP35x based products to market faster than those created on embedded open source.
Aptina Launches MT9P013 5MP Image Sensor Created for 5MP Mobile Phones
Aptina announced the launch of the MT9P013 5MP image sensor. Like the image sensor’s predecessor, the 5MP MT9P012, Aptina’s new sensor was created with the demanding mobile market in mind. To achieve the performance the quality-focused mobile market expects, the new 1.75-micron pixel, 1/3.2 inch optical format sensor leverages the same successful light-capturing technology Aptina is integrating into its 1.4-micron image sensors. The improvements to the MT9P013 1.75-micron pixel improve performance, and low-light sensitivity to enable mobile applications like cell phones to capture higher quality images.
Agilent Offers Licensing Model Dedicated to Advanced RFIC Verification
Agilent Technologies Inc. (NYSE:A) announced the industry’s first simulation licensing model dedicated to reducing the cost of advanced verification. Used with Agilent’s GoldenGate RFIC simulation, analysis and verification software suite, the new license helps manage costs and improves large-scale RFIC yield and manufacturability.
Synopsys Announces Composite Current Source Modeling Technology
Synopsys, Inc. (NASDAQ: SNPS) announced the introduction of breakthrough Composite Current Source (CCS) base curve modeling technology that reduces digital cell library file size by up to 75 percent while improving application tool runtime and capacity. Starting at 65-nanometers (nm), and becoming critical at 45-nanometers, increased process variation and low power design flows, such as multi-voltage design, require more library corners as well as more complete and accurate power modeling views, causing library file size to increase ten-fold over the previous node.