Atrenta Introduces SpyGlass Clean Flow for ESL Synthesis
Atrenta Inc. announced the expansion of its “SpyGlass® clean RTL” efforts to the ESL synthesis flow. Atrenta has formed partnerships with leading ESL synthesis tools providers Forte Design Systems, Synfora, Esterel EDA Technologies, and AutoESL Design Technologies under its SpyLinks[tm] program. The program ensures that the RTL output from the partners is compliant with SpyGlass and meets quality requirements on a wide range of issues such as coding standards, synthesizability, simulation readiness, clock management and power management.
ARM Introduces SOI Physical IP Library for IBM 45nm SOI Foundry
ARM [(LSE: ARM); (Nasdaq: ARMH)] announced the industry’s first Silicon-on-Insulator (SOI) physical IP library including standard cell, memory and I/O libraries for IBM’s fully enabled 45nm SOI foundry. As lower power levels and increased system-on-chip (SoC) performance become more difficult to achieve with a traditional bulk CMOS process, SOI technology enables up to 30 percent better performance and 40 percent power savings at existing process nodes.
Denali Software Launches Verification IP for SuperSpeed USB Interface
Denali Software, Inc. announced that its PureSpec[tm] verification intellectual property (VIP) product now supports the USB 3.0 specification from the USB 3.0 Promoter Group , allowing device and system designers to begin advanced USB 3.0 development. Denali’s PureSpec USB VIP product provides both design and verification engineers with a high-quality solution for modeling, simulating, and verifying designs that utilize the latest USB interface specification, enabling them to accelerate the design and verification of USB devices and systems.
Tokyo Electron Device Unveils of 3 inrevium FPGA PCI Express Platforms
Tokyo Electron Device Limited (TED) has announced the release of three inrevium Virtex®-5 High-Density PCI Express Platforms. These PCI Express Gen 1 & 2 capable platforms utilize Xilinx Virtex-5 LX330T, SX240T and FX200T FPGAs, the highest density FPGAs available. In recent years, high performance embedded systems require FPGAs with higher speed, density and performance.
Northwest Logic Debuts x8 PCI Express 2 Solution for Virtex-5 FXT FPGA
Northwest Logic announces the immediate availability of a high-performance, hardware-proven x8 PCI Express® 2.0 Solution for Xilinx’s Virtex®-5 FXT FPGA platform. This solution combines Northwest Logic’s full-featured x8 PCI Express 2.0 cores and software to provide a complete, pre-packaged x8 PCI Express 2.0 solution. The solution enables high-performance x8 PCI Express 2.0 designs to be quickly developed for Virtex-5 FXT FPGAs.
Aldec Mixed-Language HDL Simulator to Support OVM 2.0
Aldec, Inc. is pleased to announce that it is now an official partner on OVM World, the community site for the Open Verification Methodology (OVM). This partnership will enable Aldec to offer support for OVM 2.0, the first open, language-interoperable verification methodology, co-developed by Cadence Design Systems, Inc. (NASDAQ: CDNS). This OVM-based release of the Aldec mixed-language HDL simulator will provide the OVM community additional choices.
Advanced Fusion Modernizes Legacy Military Systems with RTI Middleware
Advanced Fusion Technologies announced that it will seamlessly integrate with middleware from Real-Time Innovations (RTI), The Real-Time Middleware Experts, to develop the industry’s first product suite designed to modernize legacy U.S. military applications by enabling them to use a modern open-system architecture. The U.S. military aims to improve its competitiveness by reducing costs and integration cycle times for delivering capabilities to warfighters.
Dini Group Selects Altera Stratix III for FPGA-Based Prototyping Board
Altera Corporation (NASDAQ:ALTR) announced The Dini Group selected the Stratix® III EP3SL340 FPGA, featuring 340K logic elements (LEs), in its DN7020K10, the industry’s largest single-board FPGA-based prototyping engine. The DN7020K10 supports 20 EP3SL340 FPGAs in 1,760-pin packages providing 1,104 user I/Os per device and a capacity of more than 50 million equivalent ASIC gates. Customers designing custom ASICs can use this ultra-high-capacity prototyping board to verify their logic designs and run them at near real-time clock speeds.