UMC (NYSE: UMC; TSE, 2303) and Mentor Graphics Corporation (Nasdaq: MENT) have developed a new series of analog/mixed-signal and RF foundry design kits (FDKs). The FDKs, containing comprehensive and validated building blocks at the transistor device level, help IC designers to jump-start design cycles on UMC’s 0.13um and 90nm MM/RF process nodes. Featuring Mentor’s analog/mixed-signal IC flow, the FDK’s will reduce time-to-market and optimize manufacturing success for analog, mixed mode and RF system-on-chip (SoC) ICs.
The comprehensive FDKs include UMC Eldo simulation models, Calibre DRC, LVS and extraction technology files, schematic symbols and programmable device generators for supporting schematic driven layout and simulation, along with a set of configuration files for customization.
Mentor’s FDKs for UMC’s advanced MM/RF process provide customers with key technology to help them achieve first silicon success. Since the FDKs are validated within Mentor’s complete mixed-signal SoC design flow, customers can gain competitive time-to-manufacturing advantages with the assurances of a proven, turn-key methodology and a proven path to silicon. The combination of UMC’s production-proven, mixed-signal and RF processes and Mentor’s world-class, optimized mixed-signal design flow will enable customers to have optimal control and predictability over their SoC design and manufacturing.
UMC’s mainstream 0.13um process employs up to 8 layers of copper interconnects to enable a gate density of 220K gates/mm2. UMC’s 90nm process has been in customer production since March of 2003, making UMC the first dedicated foundry company to announce the delivery of working customer ICs built on this technology node. UMC and Mentor Graphics will continue to extend FDK offerings to 65nm and beyond by leveraging Mentor’s IC flow, which contains a unified design platform with a centralized design cockpit that allows seamless navigation throughout the entire analog mixed-signal IC design flow, from schematic capture, simulation and floor planning, to physical layout and final verification.