News 2008.07.14 Late Edition

GSA Releases Analog Mixed-Signal Radio Frequency Process Checklist
Global Semiconductor Alliance (GSA) announces the release of its Analog/Mixed-Signal/Radio Frequency (AMS/RF) Process Checklist Version 1.0. The tool was developed by the GSA MS/RF Subcommittee’s Process Control Monitoring (PCM)/Process Checklist Working Group. The AMS/RF Process Checklist reflects the key attributes of an AMS/RF foundry process offering. It provides standard definitions for quantitative and qualitative metrics.

Numonyx Announces 65nm StrataFlash for Embedded NOR Market
Numonyx B.V. announced it has extended its family of high-density NOR flash memory products to its 65-nanometer (nm) process lithography to meet the demands of embedded customers. According to the company, the move to 65nm process technology provides price/performance balance and ensures support for extended product life cycles, both important factors to original equipment manufacturers (OEMs) designing for embedded market segments.

Advantest Launches Turn-key RF Test Cell Solution at Semicon West
Advantest Corporation (TSE: 6857, NYSE: ATE) is introducing its new, high-performance RF test cell solution at Semicon West, and is also demonstrating its new compact test solution for cost sensitive consumer devices. In its booth #7447 West, Advantest will also feature its suite of memory solutions for high-productivity, low cost-of-ownership engineering and manufacturing applications.

Delta Design Rolls Out MATRiX High Speed Test Handler
Cohu, Inc. (NASDAQ:COHU) announced that its Delta Design subsidiary, the world’s leading supplier of semiconductor logic pick and place test handlers, has launched its next generation high speed test handler, the MATRiX. The MATRiX increases productivity over previous generation tri-temperature handlers in several dimensions of performance: up to three times higher throughput, four times higher parallelism, and active thermal control per test site.

Calypto SLEC System-HLS Supports Cadence C-to-Silicon Compiler
Calypto[tm] Design Systems unveiled a new version of its SLEC System-HLS (High Level Synthesis) product that is fully integrated with Cadence® Design Systems’ new C-to-Silicon Compiler high-level synthesis technology. Calypto and Cadence joined forces to deliver a dynamic, system-level design solution that dramatically increases designer productivity by automating the C-to-Silicon Compiler and SLEC (Sequential Logic Equivalence Checker) verification flow.

Qualcomm, IMEC Team on 3D Integration Research for Wireless Products
IMEC, Europe’s leading independent nanoelectronics research institute, and Qualcomm Incorporated (Nasdaq: QCOM), a leading developer and innovator of advanced wireless technologies and data solutions, announced that Qualcomm is the first fabless integrated circuit company to participate in IMEC’s industrial affiliation program (IIAP) on three-dimensional (3D) integration.

IMEC Announces Method for Fabricating Ultra-thin Silicon Solar Cells
IMEC is developing a new method to produce ~50µm thin crystalline silicon wafers for use in solar cells. The process involves mechanically initiating and propagating a crack parallel to the surface of a Si wafer. In this way, Si foils with an area of 25cm² and a thickness of 30-50µm have already been produced. The method makes use of industrially available tools (screen printer, belt furnace) and is potentially kerf-loss free.

IMEC Fabricates 32nm SRAM Cells with FinFETs, EUV Technology
IMEC reports functional 0.186µm2 32nm SRAM cells made with FinFETs from which the contact layer was successfully printed using ASML’s full field extreme ultraviolet (EUV) Alpha Demo Tool (ADT). Applied Materials, using its most advanced deposition systems, was key to fabricating the ultra-small circuit structures. IMEC also completed the integration and site acceptance test of the EUV ADT in its 300mm clean room.

IMEC Simplified Process Reduces Cost of Double Patterning Lithography
IMEC, in collaboration with JSR Corporation, realized a simplified process using only one etch step to reduce the cost of double patterning. 32nm lines and spaces were printed with a double exposure/single etch process, effectively freezing the resist after the first exposure. This simplified process paves the way for an industrial take-up of double patterning for the 32nm technology node.

IMEC Extends Wireless ECG Patch Functionality for Cardiac Monitoring
In the framework of Holst Centre, IMEC has further extended the functionality of its wireless ECG patch for cardiac monitoring. It added wave analysis software locally on the patch node. The algorithm achieves excellent results for sensitivity and predictivity, and covers a broad range of wave morphologies. The innovative ECG patch is intended to monitor single-lead ECG in daily-life conditions, opening new perspectives for cardiovascular disease management.

Semicon West Features FOA Forum
The Fab Owners Association (FOA), the association of semiconductor/MEMs manufacturing executives and suppliers, will host a forum at Semicon West on Thursday, July 17. Structured as part of the FOA’s quarterly meeting, doors will open to the public at 2:30pm in Room of Moscone South Hall.

SVTC Technologies, Infineon, Maxim, Anadigics Join Fab Owners Association
The Fab Owners Association (FOA), the association of semiconductor / MEMS manufacturing executives and suppliers, has announced the addition of it newest device-maker members: SVTC Technologies, Infineon, Maxim, Anadigics.