MIPS MIPS32 1004K Multiprocessor IP Core

The MIPS32 1004K coherent processing system, from MIPS Technologies, Inc. (NasdaqGS: MIPS), is the industry’s first embedded multi-threaded, multi-processor licensable IP core. The multi-core offers efficiency and configurability in a multi-processing system up to four single or multi-threaded processors integrated with advanced system coherency. The 1004K core optimizes CPU performance on a shared memory system, enabling multiple functions and applications to be implemented in a single product-all running concurrently and responsively under symmetric multiprocessing (SMP)-based operating systems.

MIPS32 1004K Core

MIPS32 1004K Features

  • 1 to 4 1004K multi-threaded “base” cores (up to 8 hardware threads)
  • Coherence Management (CM) unit – the system “glue” for managing coherent operation between cores and I/O
  • I/O Coherence Unit (IOCU) – hardware block for offloading I/O coherence from software implementation on CPUs
  • Global Interrupt Controller (GIC) – system and inter-processor interrupt controller
  • Extended 256-bit interface to L2 cache controller (available separately)
  • EJTAG/PDtraceTM block for advanced debug/trace of complete coherent system

The 1004K coherent processing system helps lower SoC development costs, since for many applications, fewer processors are needed than with other multi-processor solutions. Multi-threading in each CPU provides significant performance gains over single-threaded multiprocessor offerings. A wide array of key vertical applications, including digital home entertainment, home networking and office automation, are strongly poised to benefit from coherent multi-processing using multi-threading. In addition, the 1004K core offers a broad array of options for increased design flexibility. Designers can add CPUs to scale performance for their specific application requirements. The multi-core Coherence Manager (CM), the foundation block for intelligent system coherency, is configurable for one to four single- or multi-threaded cores with an I/O Coherence Unit (IOCU) that provides optional hardware coherence for I/O peripherals to remove the overhead of implementing this function in software.

The 1004K core also provides a highly scalable performance migration path for the popular MIPS32 24K and 34K core families. Since the 1004K core is MIPS32-compliant, designers can leverage an extensive base of existing software. Two initial versions of the 1004K core family will be available this quarter: the MIPS32 1004Kc, which provides a coherent processing system using base integer cores, and the MIPS32 1004Kf, which uses integer cores plus floating point units.

More info: MIPS Technologies