News – 2008.06.04

Renesas Unveils E100 Emulator for 8- to 32-Bit CISC Embedded Systems
Renesas Technology America, Inc. announced the E100 full-spec emulator, an expansion of its extensive line of development tools for engineers designing embedded systems that use microcontrollers (MCUs). The E100 improves the system design process by offering enhanced ease of use and performance compared to currently available emulators, while providing advanced debugging capabilities. The new development tool directly addresses the need for more efficient debugging.

4DSP Introduces FM577 FPGA High Density Platform
Low power consumption without compromising performance is promised by the FM577 FPGA platform introduced by 4DSP. Aimed at the next generation of vision systems, the innovative design company has created the new PMC based on a dual ALTERA® Cyclone III FPGA devices architecture. This maximizes performance while keeping costs low.

Aptina Imaging Accelerates JPEG Performance with Scalado SpeedTags
Aptina Imaging, a division of Micron Technology, Inc. announced that it will integrate Scalado SpeedTags(TM) technology into future mobile 3 MP and above multi-megapixel SOC designs. Scalado’s technology will be included in Aptina’s SOC sensors and assists in managing the larger files produced by the high resolution image sensor improving overall JPEG image handling performance. SOCs using the new technology will be used in mobile devices, such as camera phones and PDAs.

Toshiba, Sarnoff Expand License Agreement for TakeCharge ESD Protection
Sarnoff Europe announced its expanded license partnership with Toshiba Corporation in Sarnoff’s TakeCharge® electrostatic discharge (ESD) solution. Sarnoff has developed ESD protection solutions for five consecutive generations, ranging from 180 nanometers (nm) to 45nm, of Toshiba CMOS process technologies. Under the new license agreement, solutions for 32nm and beyond CMOS technologies are expected to be developed and existing and future solutions will be available.

Extreme DA Adds MXO Capability to GoldTime Timing Analyzer
Extreme DA[tm], the emerging leader in new-generation timing analysis software, announced the addition of multi-dimensional optimization (MXO[tm]) capability to its GoldTime[tm] timing analyzer. GoldTime MXO provides the fastest way to analyze complex digital SOC designs with the smallest number of computer resources. The accuracy and completeness of timing analysis is important to ensure that complex designs will become working integrated circuits (ICs).

Synopsys Supports TSMC Reference Flow 9.0
Synopsys, Inc. (NASDAQ: SNPS) offers support for TSMC Reference Flow 9.0 targeting 40-nanometer (nm) processes. Technologies include: low power design and verification provided by the Eclypse[tm] Low Power Solution using the industry standard Unified Power Format (UPF); advanced Design-for-Test (DFT); complete 40-nm design rule support for place-and-route; transparent half-node design flow; statistical leakage analysis; and enhanced design-for-manufacturing (DFM).

CAST, SoC Solutions Build FPGA System with Synopsys ReadyIP Flow
Silicon Intellectual Property (IP) provider CAST, Inc. and technical partner SoC Solutions LLC recently proved the effectiveness of a new FPGA design capability from Synopsys’ Synplicity Business Group by developing a complete 32-bit processor-based system in just three and a half days. The system is a typical design that uses an ARM® Cortex[tm]-M1 processor and includes all the buses and peripherals needed to run embedded software..

Tensilica, SPIRIT DSP Team on Mobile Multimedia Audio, Voice for Xtensa
SPIRIT DSP, the world’s leading supplier of voice, audio and video software engines, and Tensilica,® Inc. announced that they have formed a strategic partnership and can now deliver 18 optimized, high quality digital audio and voice software packages that run on Tensilica’s HiFi 2 Audio Engine, an increasingly popular audio architecture for system-on-chip (SOC) designs.

CoWare, Doulos Team on ARM System Design Training
Doulos, the global provider of independent methodology and technology training, and CoWare® Inc, the leading supplier of platform-driven electronic system-level (ESL) design software and services, announced they will broaden the scope of their successful collaboration on SystemC and transaction-level modeling (TLM) education to encompass the market-leading Doulos ARM training capability.

GreenSocs Announces DAC Transaction-level Modeling Tutorial
GreenSocs[tm] Ltd announced it will host a technical tutorial during the Design Automation Conference 2008 in Anaheim CA. The tutorial is titled, Writing Efficient TLM 2.0 Models with GreenSocs. At this year’s Design Automation Conference, the Open SystemC Initiative (OSCI) will announce details of its new SystemC transaction-level modeling (TLM) standard for model interoperability, TLM-2.0.

EVE to Break the Billion Cycle Barrier with ZeBu at DAC
Design Automation Conference (DAC) attendees who stop by the EVE booth (#301) during the conference will learn how to “break the billion-cycle barrier” with ZeBu, EVE’s system-on-chip (SoC) hardware and embedded software co-verification solutions. Also being demonstrated will be EVE’s expanded library of standard transactors, custom transactor development software known as ZEMI-3 and DW-FPGA, a DesignWare® foundation library.

Pachira IP to Represent Innurvation for Semiconductor Patent Licensing
Pachira IP, a technical intellectual property licensing firm, and Innurvation, Inc., a medical diagnostic device company, have reached an agreement granting Pachira the exclusive right to license the semiconductor patents owned by Innurvation. The combination of in-depth semiconductor knowledge and professional negotiators with years of experience licensing semiconductor patents uniquely positions Pachira to support Innurvation’s advanced semiconductor patents.