News – 2008.01.14 Late Edition

EDA Industry Grows by 7.2% to $1,412.1 Million in Q3 2007
The EDA Consortium Market Statistics Service (MSS) announced that the electronic design automation (EDA) industry revenue for Q3 2007 grew 7.2 percent to $1,412.1 million, versus $1,317.2 million in Q3 2006. The four-quarter average growth rate, which compares the most recent four quarters to the same four quarters in the prior year, was 12.3 percent.

STARC Selects Synopsys PrimeTime VX Variation-Aware Timing Tool
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, announced that the Semiconductor Technology Academic Research Center (STARC) has incorporated Synopsys’ PrimeTime® VX variation-aware, statistical timing signoff solution as part of its 65-nanometer (nm), Synopsys-based STARCAD-CEL methodology. Because the PrimeTime VX solution is built on Synopsys’ PrimeTime static timing analysis (STA) tool — the industry’s gold standard — STARC was able to validate multiple evolutionary approaches to introducing statistical STA (SSTA) into existing design flows. As a result, mutual STARC and Synopsys customers can now improve their design margins by selecting the PrimeTime-based SSTA signoff method most appropriate for their return-on-investment parameters.

Serial ATA International Organization Announces Power Over eSATA
Serial ATA International Organization (SATA-IO), the consortium dedicated to sustaining the quality, integrity and dissemination of SATA technology, announced its Power Over eSATA initiative. SATA-IO has begun work on a new specification that will provide power to external SATA (eSATA) devices without the need for a separate power connection. Led by the organization’s Cable and Connector group, the specification is targeted for completion in the second half of 2008.

Mentor, Calypto Team on Integrated Catapult C, SLEC Design Flow
Mentor Graphics Corporation (NASDAQ:MENT) announced the availability of a new electronic system level (ESL) hardware design and verfication flow featuring Mentor’s Catapult® C Synthesis tool and Calypto Design Systems’ SLEC sequential equivalence checker. Proven during trials at customer sites throughout the world and recently by STARC, the integrated flow is effective at synthesizing high-quality designs from pure ANSI C++ to RTL, and formally verifying that the resulting RTL design is functionally correct. These customer results validate the Mentor/Calypto design flow, and indicate its readiness for broad production usage by companies using ESL methodologies for hardware design.