Renesas RX Family of Microcontrollers

Renesas Technology recently announced a new CISC (Complex Instruction Set Computer) CPU architecture. The new architecture will improve code efficiency, processing performance, and power consumption. CISC microcontrollers (MCUs) based on the new architecture will be branded as the ‘RX’ family (RX stands for Renesas eXtreme). The new RX architecture will unifying Renesas’ existing CISC architectures into a single platform. The new platform will be compatible with existing CISC products. The first of the enhanced MCUs are expected to become available in the second quarter of 2009. The primary target markets include office automation, digital consumer electronics, industrial systems, and other embedded applications.

Renesas Rx CPU Target Perfomance

The RX CPU features sixteen 32-byte standard registers and has variable-length instruction byte units. It adopts the Harvard architecture and has multiplier/dividers, as well as a built-in single-precision floating-point processing unit (FPU). The CPU makes frequently-used instructions to one or two bytes long to save code space, and has a single-cycle instruction set architecture. Renesas will offer 16-bit and 32-bit versions of the new CPU.

RX Specifications:

  • Maximum operating frequency: 200MHz
  • Processing performance (MIPS/MHz): 1.25 MIPS/MHz (Dhrystone v2.1 benchmark)
  • High code efficiency: 30% reduction in object-code size compared to existing products
  • Low power consumption: 0.03 mA/MHz

RX Highlights:

  • Fast, high-performance CPU
    The new architecture provides high-speed operation (200MHz) while at the same time processes more instructions per clock cycle: 1.25MIPS/MHz, as measured in the Dhrystone v2.1 benchmark. The new CPU is based on a Harvard Architecture, which provides separate address and data paths, allowing the execution of instructions and data access in single cycle. This single-cycle capability was also tested and verified using field-proven Renesas MCUs. To ensure the highest performance possible, Renesas has performed extensive design and testing work on the architecture. As a result, the new architecture is fully optimized with the efficient use of registers, instructions and address modes. Moreover, it has sixteen 32-bit general-purpose registers, which allow the CPU to process both data and addresses in all available registers.
  • On-chip floating point unit
    To enable highly sophisticated real-time control and multimedia applications, the RX CPU incorporates critical functions such as a multiply, divide, and multiply/accumulate. It also implements an IEEE754-compliant 32-bit single-precision floating-point processing unit (FPU) for handling multiple data types. The FPU reduces the calculation time for data processing tasks, the number of cycles needed for mathematical calculations, and the response time for any event occurrence, providing enhanced real-time performance.
  • Highly efficient use of code
    The RX CPU core has 4GB of address space and supports twelve types of address modes including Register Indirect with Index and Post Increment. The new CPU core supports byte-unit variable-length execution instructions that range from 1 to 9 bytes. It assigns 1- or 2-byte instructions to the most frequently used functions. All these enhancements compile application code in smaller program memory space, reducing overall system cost. Renesas expects that the new core will be thirty percent more code efficient compared to existing Renesas devices.
  • Low power consumption
    The newly developed 90-nm process that will be used to build the MCU with the RX architecture is a low-power, low-current-leakage technology. The improvements in logic and circuit designs help the new architecture to achieve 0.03mA/MHz or less power consumption at active mode when the CPU is running at full speed.
  • Compatibility and scalability
    To provide customers with seamless upgrade paths for higher performance MCUs or other compatible devices, Renesas plans to offer a complete suite of development tools for all devices with the RX architecture. The new toolchain is expected to simplify the migration of system designs and application code, so customers will need less time to complete new product development. The new toolchain including a C compiler will ensure the reuse of code, protecting the customers’ investments made in the H8 and M16C families.

More info:
Renesas RX CISC Microcontrollers