Synopsys DesignWare System-Level Library
Synopsys, Inc. (NASDAQ: SNPS) recently announced the DesignWare(R) System-Level Library. The library provides high-performance SystemC transaction-level simulation models (TLMs) for assembling virtual platforms, including instruction set simulators (ISS), and TLMs of Synopsys' DesignWare Cores and ARM(R) AMBA(R) interconnect components. All DesignWare System-Level Library models are written in SystemC and work in IEEE 1666 (SystemC) compliant simulation environments, making them tool- independent.
The DesignWare System-Level Library features more than 50 TLMs, including high performance models of ARM processors and models of DesignWare standards- based connectivity IP such as USB 2.0 HS OTG, SATA AHCI and AMBA interconnect components. Also included are pre-assembled models of complete platforms, such as the ARM Integrator(TM) Platform, which can be used as reference designs for driver development or as a starting point for building larger virtual platforms.
Transaction-level models are the basic building blocks required to build virtual platforms for early hardware/software co-design, architectural exploration and system verification. Virtual platforms are fast, full-function simulation models of the hardware that enable development and integration of software months before hardware is available.
DesignWare System-Level Library is available now.
More info: DesignWare System-Level Library »
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