ARC International’s (LSE:ARK) LP-RDM is a new automated Common Power Format (CPF)-enabled low-power reference design methodology. The LP-RDM has been implemented in ARChitect processor configuration tool. The LP-RDM with the Cadence(R) Low Power Solution ensures that ARC’s new Energy PRO technology is captured in RTL and implemented consistently throughout the design flow to GDSII. Users of the reference design flow may achieve up to a four-fold reduction of IP core power.
Cadence Low-Power Solution scripts are integrated into ARC’s configuration tool in a Reference Design Flow (RDF) library. ARChitect allows the designer to implement various Energy PRO features while taking advantage of Virage Logic’s Area, Speed and Power (ASAP) Logic(TM) standard cell libraries and Ultra-Low-Power standard cell architecture. ARChitect then produces RTL containing the Energy PRO design intent for input to the Cadence Encounter(R) digital IC design platform – a key component of the Cadence Low-Power Solution. Using the industry standard SI2 Common Power Format, the Encounter platform provides RTL to netlist synthesis, verification, floor planning and routing for a TSMC 90nm process technology. Thus SoC designers can easily configure an Energy PRO processor and be assured that all its low-power capability automatically propagates through the entire Encounter flow to final layout.
The new low-power reference design methodology (LP-RDM) implemented in ARChitect is available now.