News – 2007.10.25 – Late Edition

Chipworks to Tear Apart Intel Penryn Chip
Chipworks, the leader in reverse engineering and technical analysis of semiconductors and microelectronic systems, announced the arrival of the new Intel® CoreT2 processor family chips (codenamed “Penryn”) using Intel’s 45-nm process technology. The chips, not yet commercially available, are now in Chipworks’ labs and will undergo the world’s most thorough structural analysis and transistor characterization. These chips are the first to be brought to market via Intel’s new manufacturing strategy announced in 2006. The Penryn 45 nm chips are the latest devices shipped to meet Intel’s goal to maintain market leadership and performance by introducing chip microarchitectures and manufacturing technologies on a regular two-year basis.

STMicroelectronics Announces Tiny Fully-Integrated PWM Controllers
STMicroelectronics (NYSE: STM), a world leader in the supply of semiconductors for power management applications*, extended its portfolio of power management devices with a new family of flexible and high-performance PWM (Pulse Width Modulation) controllers intended for motherboard and POL (Point of Load) markets. Four new products – L6726A, L6727, L6728 and L6728A – integrate a voltage reference, control logic, gate drivers, monitoring and protection circuits into standard SO-8 or tiny 3×3mm DFN packages. Two of the chips offer additional features for high-level applications, including a PowerGOOD output to report power status and the output voltage sense for accurate over-voltage and under-voltage protection.

Advantest Introduces T5781, T5781ES Memory Test Systems
Advantest Corporation (TSE: 6857, NYSE: ATE) is introducing its new high-speed, high-throughput memory test systems for Multi-Chip Packages (MCPs). The new T5781 Test System offers high test speeds of 533Mbps for tomorrow’s MCPs, devices which combine multiple memory types — such as NAND, NOR and DRAM — in a single package. Complementing the T5781 is the new T5781 Engineering Station (T5781ES), which is designed for evaluation of devices and development of test programs in a developmental/laboratory environment. Combining DDR features and performance and flash functionality into a single platform, the T5781 offers both a fast turn-around development solution and high volume production test for tomorrow’s memory intensive applications.

Agilent, Fujitsu Create Chipset Test Solution for Mobile WiMAX
Agilent Technologies Inc. (NYSE: A) and Fujitsu Microelectronics Pacific Asia Ltd. announced the integration of Agilent’s WiMAX(TM) test solutions into Fujitsu’s chipset test solution for Mobile WiMAX, enabling the highest measurement throughput available in the industry today.

The Portland Group Optimizes PGI 7.1 for Multi-core 64-bit Processors
The Portland Group(R), a wholly-owned subsidiary of STMicroelectronics (NYSE: STM), announced the general availability of Release 7.1 of its suite of Fortran, C and C++ compilers and development tools. PGI(R) compilers and tools are used widely in high-performance computing (HPC), the field of technical computing engaged in the modeling and simulation of complex phenomena, such as ocean modeling, weather forecasting, seismic analysis, bioinformatics and other areas. PGI compilers, which convert software programs into the binary instructions that a computer can understand, are recognized in the HPC community for delivering world-class performance across a wide spectrum of applications and benchmarks, and they are referenced regularly as the industry standard for performance and reliability.

LSI, Kawasaki Test Designs with Encounter Cadence True-Time Test ATPG
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, has developed unique test technologies enabling its customers, including Kawasaki Microelectronics (K-micro) and LSI Corporation, to more cost effectively produce large numbers of high-performance, super-dense integrated circuits with extremely high quality. Building a competitive processor or an advanced system on chip (SoC) ASIC design is a daunting technological challenge. Through its leading test generation and compression technology, Cadence® Encounter® Test technology helps ensure these complex, high-performance devices work as designed.

Synopsys Announces Best Paper Awards at SNUG
Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design and manufacturing, announced the Best Paper Awards for the 16th annual Synopsys Users’ Group (SNUG®) in Munich, Germany. At the Munich event, the first place award for Best Paper went to Kees Timmermans and Simon Meintema ofTTA-International for “Automated Development of Schematic Documentation for Web-Delivery.” Second place went to Dan Steinberg of Integrated Device Technology for “Regression & Random Sims: Techniques & Recommendations.” Third place went to Jacob Andersen, Peter Jensen and Stig Kofoed of SyoSil for “Standardizing Verification IP Reuse by Introducing SystemVerilog Verification Components.”The award for Best First-Time Presenter went toJuergen Dirks of LSI Corporation for “Mix and Match of Flat, Hierarchical and Pseudo-Hierarchical Approaches for Different Steps of a Design Flow.”The winning papers were selected by the attendees and the SNUG Technical Committee.

NEC, ARC, Denali, TSMC Receives Collaboration Awards from Cadence
Cadence Design Systems, Inc. (NASDAQ: CDNS) has announced the winners of the second annual Collaboration Awards for excellence in driving design chain success. The award winners are NEC Electronics Corp., ARC International, Denali Software and Taiwan Semiconductor Manufacturing Company (TSMC). Cadence® announced the Collaboration Award winners at the annual Cadence Design Chain Partners Event, held Oct. 23 in San Jose, Calif.