DDC-I Unveils OpenArbor Real-Time Mixed Language Eclipse IDE
DDC-I, a leading supplier of development tools for safety-critical applications, announced the first Eclipse-based mixed-language development and run-time environment to integrate C, Embedded C++, Ada, and real-time Java. Known as OpenArbor, the new IDE makes it possible to develop hard real-time applications that combine Java, C, EC++, and Ada.
QuickLogic Creates System Block for SDIO Client
Underscoring its commitment to the mobile electronics market, QuickLogic® Corporation (NASDAQ:QUIK), the lowest power programmable solutions leader, released a proven system block for an SDIO client. This block, part of QuickLogic’s functional library for its Customer Specific Standard Product (CSSP) platforms, enables a range of unique accessories for mobile devices utilizing the popular SD memory card and SDIO peripheral interface.
Enea Introduces dSPEED Platform
Enea (Nordic Exchange/Small Cap/ENEA), a leading provider of network software and services, announced the availability of dSPEED Platform(TM), the first commercial high availability platform designed to manage clusters of Digital Signal Processors (DSPs).
Renesas Rolls Out SH7730 32-Bit SuperH RISC Microprocessors
Renesas Technology America, Inc. announced the SH7730 group: three 32-bit microprocessors for use in a wide range of multimedia applications, such as digital consumer products and industrial equipment. The devices strengthen the company’s popular line of SuperH® RISC (Reduced Instruction Set Computer) solutions that incorporate the fast SH-4A superscalar CPU core.
NemeriX Launches NX4 Next Generation A-GPS Navigation Platform
NemeriX, a leading provider of A-GPS semiconductor solutions, announced the release of its 4th generation A-GPS navigation platform: the NemeriX NX4. This modular, scalable, hosted & stand-alone A-GPS navigation solution directly targets the strategic roadmaps of mobile handset vendors. Like the three NemeriX GPS generations which precede it, the NX4 is designed to be an industry leader on low power and high sensitivity, provide top tier performance (e.g., tracking, TTFF time-to-first-fix), and have the lowest bill-of-materials (BOM).
Sequence Design to Host Low-Power Design Seminar in Japan
Sequence Design, EDA’s Design-For-Power (DFP) technology leader, will host its fifth low-power design seminar in Tokyo on Thursday, Nov. 8, 2007, from 12:50pm to 5:30pm at Tokyo’s Akihabara Convention Hall. This event is co-sponsored by Sequence Design, AMD Japan, Cadence Design Systems Japan, NEC System Technologies, and HP Japan.
IMEC to Conduct Research on DRAM MIMCAP Process Technology
IMEC launches research on next-generation DRAM MIMCAP (metal-insulator-metal capacitors) process technology as part of its (sub-)32nm CMOS device scaling program. This research will enable IMEC and its partners to address the material and integration requirements to scale DRAM MIMCAP to future technology generations. This newly added focus follows an earlier extension of its traditional logic- and SRAM-oriented program with a DRAM periphery transistor sub-program in November 2006. The objective of the latter sub-program is to research high-k and metal gate options sustaining a DRAM-oriented process flow.
NI Announces PXIe-6672 PXI Express System Timing Controller
National Instruments (Nasdaq:NATI) announced the latest additions to NI timing tools including the industry’s first PXI Express timing and synchronization controller and a PXI module that synchronizes PXI systems over GPS, Inter-Range Instrumentation Group (IRIG) and IEEE 1588. With these new products, engineers can achieve improved synchronization and timecode capabilities in PXI systems, which is important for synchronizing multiple systems, precisely timestamping events and improving measurement accuracy in automated test and data acquisition applications. These new timing features are integral to the development and control of large distributed systems such as particle accelerators and high-energy physics systems.
IMEC, PRC Offer Research Program for Flip-chip, Substrate Technology
The Microsystems Packaging Research Center at the Georgia Institute of Technology (PRC)-Atlanta. Ga., and IMEC invite interested parties from global industry to join their advanced research program on next-generation flip-chip and substrate technology. The program addresses the key ‘IC-to-package to board’ packaging interconnect issues for 32nm ICs and beyond.
Cypress Creates 4-Mbit nvSRAM with .13-Micron SONOS Process
Cypress Semiconductor Corp. (NYSE:CY) introduced a 4-Mbit non-volatile static random access memory (nvSRAM). The new device features access times as low as 15 ns, infinite read, write and recall cycles, and 20-year data retention, making it ideal for applications requiring continuous high-speed writing of data and absolute non-volatile data security including RAID applications, harsh environment industrial controls, and data logging functions in automotive, medical and data communications systems.
Tensilica Licenses Diamond Standard 108Mini Processor Core to MediaPhy
Tensilica®, Inc. announced that MediaPhy Corporation, of San Jose, Calif., has licensed the Diamond Standard 108Mini, the industry’s lowest power 32-bit processor core for SOC (system-on-chip) design. MediaPhy will use the Diamond Standard 108Mini in its next generation mobile audio and video entertainment designs.
Saifun Licences Pulsic Physical Design Technology
Pulsic Limited, the leader in custom design automation for memory, announced that it has entered into a long-term agreement to licence its leading-edge physical design technology to Saifun Semiconductors Ltd. Yoram Betser, Vice President of Design for Saifun, commented: “Saifun provides flash designs to some of the world’s leading flash manufacturers. After carrying out a detailed evaluation, we chose the Pulsic solution as we believe it will provide us with significant productivity gains in relation to our unique and innovative NROM memory IP.”