The Cadence (NASDAQ: CDNS) SoC Functional Verification Kit is a comprehensive verification kit for wireless and consumer system-on-chip (SoC) design. It enables engineers to adopt advanced verification techniques with reduced risk and deployment effort and meet time-to-market requirements. The Cadence(R) SoC Functional Verification Kit provides a proven end-to-end methodology that extends from block-level verification to chip- and system- level advanced verification and includes automated methodologies for implementation and management. The kit provides complete example verification plans, transaction-level and cycle-accurate models, design and verification IP, scripts and libraries—all proven on a wireless segment representative design and delivered through applicability consulting.
The new kit addresses key challenges engineers face when designing and verifying SoC designs: ensuring comprehensive verification of the design, enabling re-use, managing low-power modes typical in today’s SoCs, ensuring hardware-dependent software coverage, and accomplishing the verification within very stringent time-to-market timelines.
The applicability consulting included with the kit provides complete and interactive guidance for performing predictable and repeatable verification of blocks, clusters, full chips, and SoCs, and enables design teams to quickly and easily adopt the Cadence Incisive(R) Plan-to-Closure Methodology.
The SoC Functional Verification Kit includes design and verification IP from Cadence and third parties, including an accurate high-speed model of the ARM968E-S(TM) processor, AMBA(R) PrimeCell IP(R) including interconnect and peripherals, and the ARM(R) RealView(R) Development Suite debugger, USB 2.0 from ChipIdea, and 802.11 from WiPro. The kit includes three main flows: architectural, RTL block to chip, and system-level. Users can implement the entire kit as an integrated flow, or may select flows individually. Also included are 13 workshop modules and over 40 hands-on labs which engineers can use to incrementally improve their verification productivity.
Cadence kits enable IC designers to accelerate technology-specific product development and address design challenges in EDA technology segments such as analog mixed signal, silicon-in-package (SiP), coverage-driven functional verification, and radio frequency integrated circuit (RFIC). By using Cadence kits, customers can focus more of their design resources on design differentiation rather than developing design infrastructure.
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