ARC Video Subsystems

ARC International (LSE:ARK) set a new standard for high-quality video encoding with the introduction of five new members of the ARC(R) Video Subsystem family: AV 417V, AV 407V, AV406V, AV 404V, and AV 402V. All include ARC’s new patent-pending technology “dynamic adaptive encoding” that enables encoding of video streams at the lowest power. The products are capable of encoding and decoding up to Standard Definition resolution video using advanced video coding standards such as H.264.

ARC Video Subsystem family members enable SoC designers to quickly create unique products for a range of portable media players and tethered consumer multimedia appliances. Based on the recently introduced VRaptor(TM) Multicore Architecture, each is programmable, encodes and decodes a wide range of popular video standards, and comes with optimized media processing elements including:

  • A member of the configurable ARC 700 core family
  • Up to two 128-bit SIMD Media Processors
  • A dual-channel media-optimized DMA engine
  • Separate multi-standard encoding and decoding accelerators
  • Programmable motion estimation accelerator
  • SoC development tools
  • Optimized video codecs:
    • (encoders) H.264 BP, MPEG-4 SP/ASP, H.263 profile 0, and JPEG
    • (decoders) H.264 BP, MPEG-4 SP/ASP, H.263 profile 0, VC-1 SP, MPEG-2 MP, MJPEG, JPEG, GIF, TIFF, and PNG

With the high quality encode capability in the new ARC Video Subsystems, SoC developers can design chips that are differentiated and solve the disparate challenge of providing superior resolution encoding while consuming little power. Market opportunities for such products are booming. Research firms project the worldwide installed base of just camera phones will top 1.5 billion units by 2010, becoming the most prevalent image capture devices in the world.

The ARC Video Subsystems achieve high quality video encode by employing algorithms (“tools”) specified from standards bodies for video codecs such as H.264, which is up to five times more complex than other coding standards. Their high performance architecture (based on VRaptor) allows usage of the demanding encoding algorithms at reasonable clocking frequency resulting in a power-efficient solution.

A major innovation embodied in the new members of ARC’s Video Subsystem Family is the patent pending technology called Dynamic Adaptive Encoding. The technology encodes video optimally under any system condition. Video encoding is a repetitive task that executes a set of algorithms to encode a digitized video stream or a set of digitized still images into such standards as H.264 BP, MPEG-4 SP/ASP, H.263 profile 0, and JPEG. Dynamic Adaptive Encoding continuously evaluates system resources and adaptively applies different processing resources to achieve the optimum result. For example, dynamic adaptive encoding allows the designer to adjust the encoding process in a phone with a fully charged battery versus one running close to empty.

ARC’s Video Subsystems are uniquely optimized to the special processing needs of video and audio applications. They are as follows:

  • Programmable to handle multi-format codecs and additional user-specific applications
  • Configurable to enable maximum product differentiation
  • Pre-integrated and pre-verified to eliminate much of the software and hardware design effort
  • Efficient video encode using very low power and little silicon real estate

The new members of the ARC Video Subsystem family are based upon the recently introduced VRaptor Multicore Architecture. It is a scalable heterogeneous processor architecture that overcomes the performance challenge of low power multimedia processing. VRaptor provides three distinct classes of ARC core modules. The first class includes a configurable 700 family core, and a range of specialized SIMD multimedia processors optimized for functions such as low-pass deblocking filters and pixel transforms. The second class includes accelerators, such as entropy encoders and decoders and motion estimators. These perform multimedia processing tasks more efficiently than general-purpose, programmable cores. And the third class includes high speed DMA controllers to relieve the CPU from complex data movement often found in multimedia codecs.

Connecting VRaptor’s heterogeneous multicore resources together is its unique remote procedure invocation over communication channels capability. The 700 processor core, SIMD accelerators, DMA engine, entropy encoders and decoders, and motion estimation accelerators are all loosely coupled and operate independently of one another. The 700 processor core apportions work to each of the accelerators using a simple fire-and-forget message. The message in main memory enables a zero overhead context switch that directs the accelerator to perform a task and inform the 700 processor when complete, at which time the 700 processor immediately issues the accelerator another context switch that initiates another task. In this manner all the accelerators are kept running independently at full speed without having to await the result of any other processing resource in the system.

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