Lattice’s (NASDAQ: LSCC) 533 Mbps DDR2 SDRAM IP core is optimized for the LatticeECP2(TM) and LatticeECP2M(TM) low-cost FPGA families, as well as its high-end LatticeSC(TM) Extreme Performance(TM) FPGA family.
The Double Data Rate Synchronous Dynamic Random Access Memory Controller IP core interfaces seamlessly with industry standard DDR2 SDRAM memory devices and has been performance-tuned for Lattice FPGAs. Not only does this IP core support all DDR2 commands, it also is extremely flexible, with intelligent bank management to minimize active commands, a synchronous implementation for reliable operation and a command pipeline to maximize throughput. The most common memory configurations are supported through a combination of variable address widths for different memory devices, programmable timing parameters, byte level writing through data mask signals and burst termination.
A primary feature of the LatticeECP2 and LatticeECP2M architectures is their pre-engineered, high performance parallel I/O that supports generic LVDS standards at speeds up to 840 Mbps. By leveraging the FPGA fabric capabilities, the DDR2 SDRAM Controller IP core is able to interface at a speed of 266 MHz, resulting in a data rate of 533 Mbps: an industry first in a low-cost FPGA architecture.
The DDR2 SDRAM controller is an IPexpress(TM) User Configurable IP core. The IPexpress design flow, included as a standard feature in Lattice’s ispLEVER(R) design tool suite, allows designers to configure the core, generate netlists and simulations files, and evaluate the core in hardware before purchase.
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