Aldec’s Riviera 2007.02 is a 64-bit mixed-language design simulation environment for VHDL, Verilog, SystemVerilog, and SystemC designs. Riviera delivers proven simulation performance and accuracy for all multi-million gate HDL designs. Riviera, running in a true 64-bit mode, leverages the hardware to perform large simulation runs requiring 16 gigabytes of memory.
To further reinforce a designer’s control over the quality and speed of design verification, Riviera 2007.02 includes performance optimization for RTL and gate level simulation (1.5-2x speed improvements over the previous release), VHDL and Verilog expression coverage, mixed PSL assertion with VHDL and Verilog design blocks support, and graphical debugging tools designed specifically for large IC designs.
More info: Riviera 2007.02