Lattice Semiconductor (NASDAQ: LSCC) LatticeECP2M PCI Express x4 IP core is optimized for the LatticeECP2M(TM) low-cost FPGA family. Like the previous PCI Express x1 IP core for LatticeECP2M devices, the x4 version implements a single-chip PCI Express endpoint solution with integrated SERDES that is ideal for high-volume, low-cost and limited form-factor applications.
Lattice’s PCI Express x4 solution includes the IP core, an evaluation board, demonstration software, and drivers. Lattice is the only FPGA supplier to offer single-chip PCI Express solutions with on-board SERDES in both low-cost (LatticeECP2M) and high-end (LatticeSCM(TM)) FPGAs. LatticeECP2M and LatticeSCM evaluation boards are both available in the PCI Express mechanical form-factor compatible with standard motherboards. The demo software utilizes the evaluation boards to demonstrate PCI express endpoint operation, including configuration, memory/register access and simple tests. Demo drivers and API also are available for users who wish to extend the demo capabilities.
The LatticeECP2M and IP core offer an innovative approach for PCI Express protocol implementation. The LatticeECP2M core implements the transaction, data link and most of the physical layer in soft IP. The remainder of the physical layer – including clock tolerance compensation, 8b/10b encoding and link synchronization – is completely embedded in the low-cost LatticeECP2M Physical Coding Sublayer (PCS), which fully supports 2.5 Gbps operation. As a result, with the LatticeECP2M core, customers benefit from a high-performance and fully integrated PCI Express solution combined with low-cost PCS/SERDES: a compelling value for high-volume applications.
The LatticeECP2M device family offers additional capabilities that enable single-chip PCI Express solutions. On-board Phase Lock Loops (PLLs) support Spread Spectrum Clocking (SSC) for the system-supplied 100 MHz PCI Express clock and enable direct conversion to the 250 MHz reference clock, while the device remains within PCI Express version 1.1 jitter specifications. This eliminates the need for any external PHY, clock conversion or attenuation chips, driving system cost lower. The combination of lower system cost and single-chip capabilities makes the LatticeECP2M device an attractive alternative to the difficulties posed by other PCI Express offerings, such as competitive FPGAs that require external chips to implement clocking, or off-the-shelf ASSP chips that offer no programmability.
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