News – 2007.05.09

Embedded Technology Forum Targets Machine Designers
National Instruments (Nasdaq:NATI), SolidWorks Corporation and Wind River announced the 2007 Embedded Technology Forum for Machine Designers, a one-day complimentary forum on embedded system design that offers an overview of technologies for reducing machine design cost and risk. Attendees will explore techniques for mechatronics-oriented design with SolidWorks(R) 3D CAD software, COSMOSMotion, National Instruments LabVIEW and Wind River VxWorks; electromechanical sensing and actuation; graphical programming for embedded systems; and remote monitoring and support.

Mentor Graphics TestKompress ATPG Tool Targets Delay Defects with SDQM
Mentor Graphics Corporation (Nasdaq: MENT) announced with the Semiconductor Technology Academic Research Center (STARC) that Mentor’s ATPG tool, TestKompress(R), will be used to target small delay defects using the Statistical Delay Quality Model (SDQM). STARC, a research consortium co-founded by eleven major Japanese semiconductor companies, developed the SDQM to enable scan-based automatic test pattern generation (ATPG) to detect small delay defects that could become more prevalent at technology nodes of 90nm and below.

SILEX Launches Embedded Biometric Fingerprint Sensors
SILEX TECHNOLOGY America, Inc. announced the unveiling of the E1 and E3, two new biometric fingerprint sensors that can be embedded into hardware to limit access and potential data theft. “Placing a permanent sensor on a machine, such as a laptop, printer or even a forklift, is the best way to regulate access to it,” said Gary Bradt, SILEX vice president, biometrics division. “With the E1 and E3, our customers can rest easy knowing that unless an authorized finger slides across the sensors, no one will ever be able to gain access to critical information and processes.”

Lightspeed Logic Creates Reconfigurable Logic for TSMC 90nm Process
Lightspeed Logic, the leading provider of mask reconfigurable IP and a member of the ARM Connected Community, announced immediate availability of the LTA90, a standard cell based reconfigurable logic IP for TSMC’s 90 nanometer (nm) G, LP, and GT logic processes. The 90nm standard tile and library are based on pre-characterized, pre-qualified ARM(R) standard cell libraries, part of its family of Artisan(R) physical IP, and are approved for use by any ARM authorized customer using TSMC as a foundry. Lightspeed Logic’s Reconfigurable Logic IP significantly reduces design cost and speeds time-to-market for families of SoC or ASSP devices. Customer usage includes such high volume markets as image processing, hand-held consumer, and flat panel TV.

Arasan Ships Next Generation SDIO neX Software Stack for SDIO IP
Arasan Chip Systems, Inc. (“Arasan”), a leading supplier of reusable Intellectual Property (IP) cores, software, semiconductors and design services, announced its is shipping its next generation SDIO software stack called SDIO neX. SDIO neX supports SD, SDIO and MMC cards with multiple host slots running on the SDIO Host and SDIO Device Controller IP from Arasan. An enhanced version supports the MMC 4.2 Card and CE-ATA micro-drive standards running on the SDIO Combo Controller IP. The stack uses and entirely new architecture designed for maximum throughput and low CPU overhead. Throughput over the SD Bus has limited the adoption of the standard in high speed applications. SDIO neX software will eliminate this bottleneck. The stack is fully compliant with the Standard SD host Controller Specification Version 2.00 from the SD Association with support for Advanced DMA 2. The software stack is optimized to work with the SDIO Host and SDIO Device IP from Arasan. The stack and bus driver are fully compatible with Linux Kernel 2.6 and can be ported easily to other embedded Operating Systems (OS) like ThreadX and VxWorks running on different processor platforms.

Optimal Adds Features to PakSi-E IC Package, SiP, PCB Design Tool
Optimal Corporation(TM) announced expanded capabilities to its flagship PakSi-E, quasi-static electro-magnetic analysis software for integrated circuit (IC) package, System-in-Package (SiP) and printed circuit board (PCB) design. PakSi-E’s performance has been improved by approximately 3X across a range of designs with no sacrifice in accuracy. Other improvements include a newly integrated CAD front-end, an overhauled and modernized graphical user interface (GUI), and Linux and 64-bit support.

GateRocket RocketDrive Blasts Off with Verific’s HDL Component Software
GateRocket(TM) Inc. announced it selected Verific Design Automation’s hardware description language (HDL) Component Software to serve as the front end to the newly launched RocketDrive(TM) Device Native(TM) verification solution for advanced FPGAs. The HDL Component Software from Verific includes SystemVerilog, Verilog and VHDL parsers, analyzers and elaborators. It is used in a variety of Electronic Design Automation (EDA) tools for exploring, navigating, analyzing, documenting and modifying large designs, both field programmable gate array (FPGA) and application specific integrated circuit (ASIC) or application specific standard product (ASSP). Written in platform-independent C++, the software compiles on Solaris, HP-UX, Linux and Windows platforms. All products are licensed as source code and come with online support and maintenance.

HP Compaq Notebooks Sense Touch with Cypress’s PSoC CapSense
Cypress Semiconductor Corp. (NYSE:CY) announced that its PSoC(R) CapSense enables the touch sensing interface inside multiple HP Compaq Notebook PC models. The Cypress CapSense solution not only provides the interface for a smooth, glitch-free user experience, but it also controls LED indicator lights on the notebooks, saving board space and reducing costs.

ISaGRAF Receives IEC 61499 Compliance Confirmation
ICS Triplex ISaGRAF Inc., the leading automation software partner, is proud to announce that their award-winning ISaGRAF automation software has received confirmation of IEC 61499 compliance from TÃœV Rheinland. Version 5.1 of ISaGRAF has been confirmed by TÃœV Rheinland to be compliant with the requirements detailed in the IEC 61499 standard. The IEC 61499 standard defines the method for designing and implementing robust and efficient cooperating systems, and presents guidelines for the use of function blocks in distributed industrial process, measurement and control systems.

GE Fanuc Embedded Debuts Data Acquisition, Signal Conditioning Systems
Broadening still further the company’s range of data acquisition and signal conditioning solutions, GE Fanuc Embedded Systems announced the DaqScribe DSC-2200 series of signal conditioning systems and the DSC-2200.Net network-centric data acquisition systems. Housed in compact 2U rack mount enclosures, both systems are designed to offer low cost yet high performance with maximum ease of use.

Xilinx Keynotes IET and FSA International Semiconductor Forum
Xilinx, Inc. (Nasdaq: XLNX) announced that Chairman, President and CEO Wim Roelandts will deliver a keynote address titled “Winning in Today’s New Semiconductor Landscape” on Monday, May 14 from 9:30 to 10:15 a.m. at the IET & FSA International Semiconductor Forum. Roelandts will provide an overview of industry trends driving consumerization of silicon, such as the “triple play” convergence of voice, video and data in today’s core infrastructure, and will describe critical success factors fabless companies must employ to win in today’s global market place.