News – 2007.04.16 – Late Edition

EVE Introduces ZeBu-AX Next-Generation Hardware Accelerator
EVE, supplier of the broadest selection of hardware-assisted verification solutions including acceleration, fast emulation and prototyping, unveiled ZeBu-AX, the next-generation hardware accelerator, designed for ease of use and offering close to unlimited capacity. ZeBu-AX has become part of EVE’s family of hardware-assisted verification solutions through EVE’s recent acquisition of Tharas Systems Inc. A full product roadmap with details about its family of accelerators to fast emulators and prototyping solutions will be unveiled in June 2007.

CAST Announces JPEG-LS Encoder Core
Semiconductor intellectual property (IP) provider CAST, Inc. announced that it has expanded its family of image compression IP products with a new lossless compression core using the JPEG-LS standard. The company believes that this is the only commercially-available JPEG-LS IP core. This addition makes CAST’s family of JPEG cores the most complete from any single vendor, featuring a mix of encoders, decoders, and codecs for the JPEG, lossless JPEG, JPEG-LS, and JPEG 2000 standards.

Mentor Graphics Rolls Out Veloce Verification Platforms
Mentor Graphics Corporation (Nasdaq: MENT), announced three new next-generation hardware-assisted verification platforms. The Veloce(R) Solo, Trio and Quattro products are based on a new Emulation-on-Chip architecture enabling megahertz-class verification run-time speeds without compromising debug productivity and modeling accuracy for designs up to 128 million ASIC gates. This new verification family delivers the industry’s fastest “target-less” and in-circuit emulation (ICE) capability that facilitates concurrent hardware-software validation and embedded system verification for key vertical market applications such as multimedia/graphics, computing, networking and wireless designs.

ARC Lowers Power Consumption of Configurable Subsystems, Cores
A member of the Power Forward Initiative and a leader in low power system-on-chip (SoC) design, ARC International (LSE:ARK) announced it is building a new design flow that will enable SoC designers to further lower the power consumption of its configurable subsystems and processors. The new reference methodology is one of the first to be created leveraging Si2′s Common Power Format (CPF) standard, and it will implement several low power features of Virage Logic’s Area, Speed and Power (ASAP) Memory(TM) instances and ASAP Logic(TM) standard cell libraries. The new flow is being integrated into the patented ARChitect(TM) configuration tool, and is expected to be available to ARC customers in the second half of 2007.

Apache Debuts RedHawk-ALP Low Power Solution for 65, 45nm Designs
Apache Design Solutions, the technology leader in power sign-off and complete silicon integrity platform solutions for system-on-chip (SoC) designs, announced RedHawk-ALP, a physical power integrity solution for advanced low power and leakage control designs. RedHawk-ALP targets power savings and leakage control techniques used in 65/45nm designs including…

eSOL PrKERNELv4 RTOS Powers EXILIM Digital Cameras
eSOL announced that its Real-time Operating System, PrKERNELv4, was selected for Casio’s newest “EXLIM Hi-ZOOM EX-V7″ and “EXILIM ZOOM EX-Z1050″ models, which went on the market February 23, 2007. PrKERNELv4 provides core management features for the complete digital camera system, including task management, memory management and real-time processing. PrKERNELv4, full of eSOL’s RTOS technical expertise and know-how, helps to realize superior real-time features and high system reliability.

Magma, Mentor Implement Unified Power Format Compliant Design
Magma(R) Design Automation Inc. (Nasdaq: LAVA) and Mentor(R) Graphics Corporation (Nasdaq: MENT) announced the successful implementation and verification of a design in which low-power requirements were specified in the Unified Power Format (UPF). Based on Magma’s Talus(TM) IC implementation platform and Mentor Graphics’ Questa(TM) verification platform, the flow has been shown to reduce turnaround time for advanced low-power nanometer (nm) integrated circuits. It is the first complete flow to support the new standard. This interoperable, UPF-compliant implementation and verification flow will be showcased at the conclusion of Accellera’s Low Power Workshop at the Design, Automation and Test in Europe conference in Nice.

Microchip Rolls Out Low-Power Op Amps
Microchip Technology Inc., a leading provider of microcontroller and analog semiconductors, announced it has expanded its linear product portfolio into the low power, high-precision arena with the MCP6031, MCP6032, MCP6033 and MCP6034 (MCP603X) operational amplifiers (op amps). The new, sub-microampere amplifiers have a quiescent current of only 900 nA and a bandwidth of 10 kHz, with a maximum voltage offset of just 150 µV at 25 degrees Celsius. The highly accurate amplifiers are ideal for handheld, portable electronic devices used in the medical, industrial and consumer markets.

Splashpower Models with Synopsys’ Saber Simulator
Synopsys, Inc. (Nasdaq:SNPS) announced that Splashpower, a U.K. innovator in wireless systems design, has chosen Synopsys’ Saber(R) mixed-signal, multi-domain simulator to develop its wireless charging system targeted for portable consumer electronics devices. Splashpower engineers chose the Saber simulator solution because of its ability to easily model and simulate the complex electro-magnetic environment of their advanced wireless power transmission system.

Harris Selects Altera Stratix II GX FPGAs for Video Broadcast Router
Altera Corporation (NASDAQ: ALTR) announced that Harris Corporation (NYSE: HRS) has selected the Stratix(R) II GX-based development kit and 3-Gbps serial digital interface (SDI) intellectual property (IP) MegaCore(R) function to reduce development time by several months for their recently introduced line of Platinum(TM) video broadcast routers.

NEC Joins In-Sequence Technology Partner Program
NEC System Technologies, Ltd. (NEC-ST) has joined the In-Sequence Technology Partner Program, promoting EDA interoperability and advanced design methodologies. As a result of the newly formed partnership, the companies have interfaced NEC-ST’s CyberWorkBench ESL synthesis with Sequence’s PowerTheater to offer users ESL productivity combined with an ability to analyze various architectures for performance, area, and power. The integrated solution is currently under development.