Xilinx ISE WebPACK 9.1i

Xilinx’s Integrated Software Environment (ISE(TM)) WebPACK(TM) 9.1i is the latest version of the company’s free downloadable programmable logic design suite. The new version includes all the features of the 9.1i release of the popular Xilinx ISE Foundation(TM) software with full support for optional embedded, digital signal processing (DSP) and real-time debug design flows. Most notably, ISE WebPACK 9.1i software includes the new Xilinx SmartCompile(TM) technology, which significantly improves run times by up to 6x faster than the previous version, while maintaining exact design preservation of unchanged logic.

ISE WebPACK 9.1i software also includes support for all devices in the Spartan(TM)-3A family of FPGAs and select Virtex(TM)-4 and Virtex-5 FPGA devices. New power optimization features help designers reduce dynamic power by an average of 10 percent.

ISE WebPACK 9.1i software offers a complete front-to-back FPGA design solution allowing users to immediately begin projects. By providing integrated tools for HDL entry, synthesis, implementation, and verification in a free downloadable environment, ISE 9.1i helps users rapidly achieve design goals while reducing overall project cost. This release includes ISE Simulator Lite on both Windows and Linux. The free MXE-III Starter version is available for download from the Xilinx website giving designers a choice in free HDL verification solutions. Xilinx delivers the industry’s lowest-cost and lowest-power FPGA and CPLD solutions with the most extensive front-to-back Windows and Linux support of any major PLD vendor.

ISE WebPACK 9.1i software includes new SmartCompile technology to help designers address the problems associated with re-implementing an entire design with each incremental change. Such re-implementations take time and introduce risk of disrupting portions of the design not directly involved with the change. Xilinx SmartCompile technology addresses these issues with the following technologies:

  • Partitions: minimize effects of minor changes late in design cycles with copy-and-paste functionality that automatically provides exact preservation of existing placement and routing and reduces re-implementation time.
  • SmartGuide(TM): reduces time for re-implementation for small changes by leveraging prior implementation results.
  • SmartPreview(TM): enables users to pause and resume place-and-route process and save intermediate results to evaluate design state. By previewing implementation information such as routing status and timing results, users can make important trade-off decisions without waiting for complete implementation.

ISE WebPACK 9.1i software also addresses the increasing sophistication of FPGA designers with a number of user interface enhancements including:

  • Tcl command console to easily transition from the ISE software graphical user interface to a command line environment.
  • Source code compatibility function identifies the files necessary to recreate results, which can be imported and exported for source control.

New features in ISE WebPACK 9.1i software build on the capabilities of Fmax technology, especially designed to deliver unparalleled performance and timing closure results for high density, high performance designs. ISE WebPACK 9.1i software includes integrated timing closure flow which incorporates enhanced physical synthesis optimizations to provide higher quality of results.

ISE WebPACK 9.1i software includes the expanded timing closure environment of the standard ISE 9.1i version – a virtual ‘Timing Closure Cockpit’ – that enables intuitive cross-probing between constraint entry, timing analysis, floorplanning and report views so designers can more easily analyze timing problems. The integrated timing closure flow incorporates enhanced physical synthesis with improved timing correlation between synthesis and placement timing, resulting in higher quality of results.

New power optimization in Xilinx Synthesis Technology (XST) and placement, together with improvements in routing, deliver an average of 10 percent lower dynamic power for the Spartan-3 generation of FPGAs. Power optimization improvements in XST also provide power-aware logic optimizations for macro processing on blocks such as multipliers, adders and BRAMs. Implementation algorithms deploy power-efficient placement strategies and lower capacitance nets within the device to minimize power without sacrificing performance.

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