News – 2007.03.12

EtherWaves Acquires Digital Radio Technology from Sonarics Labs
EtherWaves announced that it has completed the acquisition of all the assets of Sonarics Labs, a company specializing in Digital Audio Broadcasting (DAB)/Digital Multimedia Broadcasting (DMB) technology. Sonarics Labs’ proven solutions have empowered thousands of Digital Radio receivers, around the world, in the Consumer Electronics market, and in German Luxury in-car infotainment systems.

Altera Receives Military Certification for Structured ASICs
Altera Corporation (NASDAQ: ALTR) announced that the U.S. Department of State has certified that the company’s HardCopy(R) II structured ASIC design and manufacturing flow is compliant with International Trade in Arms Regulations (ITAR). Compliance allows designers of U.S. military electronics systems to take advantage of a secure HardCopy II design flow for prototyping in an FPGA and then seamlessly migrating to a structured ASIC.

Lattice Ramps Up Production of LatticeECP2-50, Lattice ECP2-12 FPGAs
Lattice Semiconductor Corporation (NASDAQ: LSCC) announced that its LatticeECP2(TM)-50 and Lattice ECP2-12 FPGA devices have been fully qualified and released to volume production. The second-generation LatticeECP2 “EConomy Plus” Field Programmable Gate Array (FPGA) families have been produced on 90nm Fujitsu CMOS technology utilizing 300mm wafers. Final characterization also confirmed the operation of the devices’ Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) memory interfaces at 533Mbps, the industry’s fastest rate in a low-cost FPGA.

Aldec, Actel Debut CoVer Co-verification Solution for ARM-based FPGAs
Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced the release of CoVer(TM), a Windows(R)-based hardware/software co-verification solution, for Actel Corporation (Nasdaq: ACTL). Easing hardware and software integration for engineers using Actel’s field-programmable gate arrays (FPGAs) with an ARM processor, such as Actel’s CoreMP7 soft ARM7(TM) core, CoVer provides control and visibility across engineering teams, which translates into shorter design schedules and lower project costs.

Lattice Debuts 533 Mbps DDR2 SDRAM Controller for Low-Cost FPGAs
Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the immediate availability of the industry’s first 533 Mbps Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) controller Intellectual Property (IP) core supporting a Low-Cost Field Programmable Gate Array (FPGA) family. This DDR2 SDRAM IP core is optimized for Lattice’s award winning LatticeECP2(TM) and LatticeECP2M(TM) low-cost FPGA families, as well as its high-end LatticeSC(TM) Extreme Performance(TM) FPGA family.

Analog Devices Unveils New Blackfins for Portable, Networked Apps
Analog Devices, Inc. (NYSE: ADI) is expanding its Blackfin’ line with the ADSP-BF52x family, a scalable series of processors optimized for performance-demanding portable applications including portable media players (PMPs), voice over IP (VoIP) phones, IP cameras, and mobile TV devices.

TI Partners with Ramtron on 130nm FRAM Process
Texas Instruments (TI) (NYSE: TXN) and Ramtron International Corporation (Nasdaq: RMTR), a leading supplier of nonvolatile ferroelectric random access memory (FRAM) and integrated semiconductor products, announced a significant milestone in the development of FRAM technology that has resulted in a commercial manufacturing agreement for FRAM memory products. The agreement provides for the production of Ramtron’s FRAM memory products on TI’s advanced 130-nanometer (nm) FRAM manufacturing process, including Ramtron’s 4-Mb FRAM memory announced concurrently in a separate press release. Ramtron and TI have been working together since August 2001, when the companies entered into a FRAM licensing and development agreement.

Mentors Offer Co-Verification Support for MIPS32 34K Processor Cores
Mentor Graphics(R) Corporation (Nasdaq:MENT) announced a new processor support package (PSP) for the MIPS32(R) 34K(TM) family of processor cores. Developed jointly with MIPS Technologies, this new C-based PSP supports transaction-level (TLM) and register-transfer level (RTL) simulation to give engineers a consistent platform upon which to view, validate and co-verify the multi-threaded hardware/software interactions occurring on the 34K processors.

RTI Data Distribution Service Middleware Supports IPv6
Real-Time Innovations (RTI), The Real-Time Middleware Experts, announced that it has incorporated Internet Protocol version 6 (IPv6) support into its RTI Data Distribution Service middleware. RTI Data Distribution Service now allows distributed applications to simultaneously support both IPv6 and the current-generation IPv4, easing migration to the newer standard. IPv6 support is required of all U.S. Department of Defense networks and applications starting in 2008, making it essential for engineers to begin adoption of this wide-ranging standard.

Novas Siloti VE Software Gains Timing-Accurate Simulation Replay
Novas Software, Inc., the leader in debug and visibility enhancement solutions for complex chip designs, introduced new timing-accurate simulation replay capabilities with an add-on module to its award-winning Siloti(TM) Visibility Enhancement (VE) software. The patent-pending Siloti Replay technology makes the process of detecting, isolating, and fixing the source of timing problems using gate-level simulation much more efficient. The new Siloti Replay module yields significantly faster simulation times and 10X smaller dump file sizes when compared to traditional methods, while also providing the accurate results needed to debug timing issues that arise during chip implementation.

MicroTuner Rolls Out MT2170 DOCSIS 3.0 Wideband Tuner
Leveraging both its experience and expertise as a leading silicon tuner supplier to the cable market, Microtune(R), Inc. (Nasdaq:TUNE) introduced the MicroTuner(TM) MT2170, the industry’s first 1-gigahertz (GHz) input tuner based on the new CableLabs(R) DOCSIS(R) 3.0 specification. Microtune’s new tuner chip is engineered to deliver the impressive data speeds (greater than 160 Mbps) and wider bandwidth (100 MHz) demanded by cable equipment manufacturers for an easy, reliable, and cost-effective way to implement DOCSIS 3.0.

PSS, MP2 Team on Mobile Point of Sale Solutions
MP2 Solutions announced that PSS Point of Sale Systems Services (pss), a MP2 Solutions Authorized Partner, will work directly with MP2 to help customers develop their comprehensive plans for adding mobile data acquisition solutions to their operations. Authorized Partners for MP2 are carefully selected for their technology expertise and their market presence.

RadioScape Extends SDR to Mobile TV, ADI’s Blackfin Processor
RadioScape plc is extending its leadership in Mobile TV broadcast technology with the addition this year of solutions for Mobile TV receivers, which will be based on the latest additions to the Blackfin(R) processor family from Analog Devices (ADI). These new, high performance, low power processors will enable RadioScape to integrate the DAB baseband decoder and the audio video decoder onto a single platform. This provides a clear saving in costs while being very competitive on space and power compared to the conventional approach today of having these on two separate chips.

RadioScape SDR Solutions to Support Additional DSP Platforms
RadioScape announced that it plans to extend the range of programmable semiconductor platforms that will support its proven software radio solutions. Having already had significant success in developing a broad range of software, module and subsystem solutions for the DAB digital radio market based on Texas Instruments DSP’s, the company believes that in emerging digital radio segments there will be demand for its proven stacks and applications for DAB, DMB, DAB-IP, DRM, FM and AM on other platforms. The first of these will be the Analog Devices Blackfin(R) BF52x series of processors.

Xcerion to Roll Out Free XML Internet OS
Northzone Ventures has invested 10 million US dollars in Xcerion AB first-round VC funding to launch its collaborative XML Internet OS. Xcerion aims to distribute the OS and accompanying applications free as a massive service over the Internet.

Tensilica Selects Tallika as Authorized Design Center
Tensilica(R), Inc. announced that Tallika Corp., of Mesa, Ariz., is now an authorized Design Center partner for customers using the Xtensa(R) configurable processor in their system-on-chip (SOC) designs. Tallika offers concept-to-production professional services serving OEMs in networking, consumer, storage and computing markets as well as digital and mixed-signal semiconductor companies.