The Aldec Active-HDL Lattice Designer Edition Lite is a FPGA design tool. It supports mixed VHDL and Verilog simulation for Lattice’s leading FPGA devices, including the 90nm Extreme Performance(TM) LatticeSC(TM) family as well as the 90nm LatticeECP2M(TM) family, which is the industry’s only low-cost FPGA family with unequaled on-chip memory capacity and 3.125 Gbps SERDES I/O.
In addition to mixed VHDL and Verilog RTL and Timing Simulation, Active-HDL Lattice Designer Edition Lite also will include Aldec’s HDL Text Editor, Language Assistant, State Machine Editor, Block Diagram Editor and other point tools in a single design workspace. Key debug capabilities such as Code Execution Tracing and Advanced Breakpoint Management also are included in the Lattice edition.
Price and Availability
Active-HDL Lattice Designer Edition Lite is available from Lattice now. The list price of $1249 for an annual node-locked license makes the Active-HDL Lattice Designer Edition Lite the industry’s superior mixed-language simulator value.