SynaptiCAD VeriLogger Extreme Verilog 2001 Simulator

VeriLogger Extreme, from SynaptiCAD, is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information and supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx.

VeriLogger Extreme comes bundled with SynaptiCAD’s graphical Verilog/VHDL integrated development environment, BugHunter Pro, which supports debugging with all major HDL simulators. BugHunter supports source-level debugging, a waveform compression engine for high-speed waveform dumping and viewing, and graphical test bench generation features for rapidly testing HDL models. BugHunter also supports importing and exporting simulation test vectors to Agilent and Tektronix pattern generators and logic analyzers.

VeriLogger Extreme has been optimized for low memory usage, enabling even very large designs to run on memory-constrained laptops. VeriLogger Extreme uses 20% less memory than SynaptiCAD’s existing interpreted Verilog simulator, VeriLogger Pro, which itself uses less memory than any other simulator on the market. Speed-wise, VeriLogger Extreme is 8x faster than VeriLogger Pro for RTL-level simulation and 30x faster for gate-level simulation. Existing VeriLogger Pro customers with maintenance contracts can upgrade to VeriLogger Extreme for free.

VeriLogger Extreme is available on Linux, Solaris, and MS Windows. A perpetual license sells for $4000 on Windows. Leasing options are also available, as well as a free, design-size limited version for student and classroom usage.

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