Lattice LatticeECP2/M FPGA Family

The LatticeECP2/M(TM) FPGA family is the industry’s first low cost FPGAs offering high-speed embedded SERDES I/O plus a pre-engineered Physical Coding Sublayer (PCS) block. Based on the innovative LatticeECP2(TM) low cost architecture, the new LatticeECP2/M family also has been developed on advanced 90nm CMOS technology utilizing 300mm wafers. Previously, high-speed embedded SERDES serial I/O with speeds over 3Gbps has been available only on relatively expensive high-end FPGAs. Integrating this capability into a low cost FPGA fabric makes this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video, and industrial equipment. Priced at approximately one-third the cost of competitive SERDES-based FPGAs, the ECP2M FPGA family effectively bridges the price/performance gap between low cost and high-end FPGAs.

The LatticeECP2/M devices also have dramatically increased on-chip memory capacity to support higher bandwidth, SERDES-based applications. LatticeECP2/M Embedded Block RAM capacity ranges from 1.2 Mbit up to 5.3 Mbits, representing up to a 400% increase over competitive low cost architectures. The LatticeECP2M FPGA family offer a comprehensive array of features that includes 375 MHz block level performance, 18×18 multipliers, embedded memory, pre-engineered 400 Mbps DDR2 memory interface support, full-rate (10Gbps+) SPI4.2 support, configuration bitstream encryption and dual-boot configuration support. With the addition of 4 to 16 channels of 3.125 Gbps SERDES, the LatticeECP2/M FPGAs are an innovative response to the broad range of customers who have been clamoring for low cost SERDES capability for PCI Express and Ethernet based chip-to-chip and small form factor backplane applications.

Key Features

  • Optimized FPGA Architecture for Low Cost Applications
    • Feature set optimized for high-volume, low-cost applications
    • Low cost TQFP, PQFP and BGA packaging
    • Up to 5.3Mbit Block RAM on LatticeECP2M and 1.1Mbit on LatticeECP2
  • 3.125Gbps Embedded SERDES (ECP2M only)
    • Low 100mW power per channel
    • Supports PCIexpress, Ethernet (1GbE and SGMII) plus multiple other standards
  • sysDSP Block
    • High performance multiply, addition, subtract and accumulate
    • Support widths of up to 36×36
  • Pre-Engineered Source Synchronous I/O
    • Simplifies implementation of interfaces such as DDR1/2, SPI4.2 and general purpose ADCs
    • Supports DDR1/2 at 400Mbps, SPI4.2 at 750Mbps and generic interfaces up to 840Mbps
  • Enhanced Configuration Options
    • Configure from SPI, JTAG or microprocessor interfaces
    • Bitstream encryption and dual boot support
    • TransFR I/O for simple field upgrades
  • ispLeverCORE Intellectual Property
    • Speed up your design cycle with ispLeverCORE Intellectual Property
  • ispLEVER Design Tools
    • Easy to use SW package supports all Lattice FPGA and programmable logic devices
    • Evaluation boards available to test your FPGA designs
  • LatticeECP2/M Applications
    • LatticeECP2/M devices are ideal for a variety of applications in cost sensitive markets such as Consumer, Automotive, Medical & Industrial, Networking and Computing

More information is available on the Lattice site.