Structured ASICs bridge the gap between standard-cell ASIC technology and FPGAs, offering low unit costs combined with faster development times. Structured ASICs start with standard, pretested base layers of logic and hard IP, and the proprietary design is then implemented on the top few metal layers. HardCopy structured ASICs are the only devices to offer a seamless prototype-to-production process for guaranteed success. Use your existing design environment to use Altera’s Stratix FPGAs series as your design’s front end and then test it in-system. When you’re done, Altera’s HardCopy Design Center seamlessly migrates your design to HardCopy structured ASICs in seven to eleven weeks.
- HardCopy II
The 1.2-V, 90-nm HardCopy II family builds on the success of Altera’s first two generations of structured ASICs. Using Stratix II FPGAs for prototyping and testing, and then migrating to HardCopy II devices, you are guaranteed success with your high-volume production devices. HardCopy II devices offer 2.2 million ASIC gates for logic prototyping, 8.8 million bits of memory, and over 350-MHz system performance. Compared to the FPGA prototype, HardCopy II devices offer over 50% core power reduction at as little as one-tenth the cost. HardCopy II devices are built on a fine-grained architecture designed for low cost that is made up of an array of HCells. The HCell architecture supports seamless FPGA migration while providing the density, cost, performance, and power benefits of ASIC technology.
- HardCopy Stratix
Altera’s HardCopy Stratix family is manufactured on 1.5-V, 130-nm process technology. These devices use Stratix FPGAs for prototyping and have the same LE architecture as Stratix devices. With 300,000 to 1,000,000 ASIC gates and up to 5,600,000 bits of memory, HardCopy Stratix devices offer a 50 percent performance increase and 40 percent lower power consumption than the Stratix prototype. HardCopy Stratix devices support a wide range of high-speed interfaces—including the SPI-4 Phase 2, 10-Gigabit Ethernet XSBI, and RapidIO interfaces. HardCopy Stratix devices also support the LVDS, LVPECL, and HyperTransport high-speed I/O standards. These advanced capabilities allow designers to connect high-speed memory devices like QDR and zero-bus turnaround (ZBT) SRAMs.