CLK Design Automation

CLK Design Automation, Inc. was founded in 2004 by an experienced team of electronic design automation (EDA) professionals. The team includes timing, signal integrity and architecture expertise from Intel, Freescale, Cadence Design Systems, Synopsys, and Chrysalis. CLK Design Automation develops static timing and power analysis tools for the design of high-performance microprocessors and advanced semiconductors. The company's breakthrough architecture delivers 10x to 100x throughput improvement over current analysis tools, largely due to its unique method of applying the performance benefits of multi-core computing platforms to its software solutions.

The Amber(TM) Analyzer removes the barriers to achieving design closure in three ways: threaded processing, incremental analysis, and advanced functionality for its complete range of analysis options (timing, signal integrity, statistical timing, leakage and statistical leakage).

The strength of the Amber solution is that it scales with both computing platform and semiconductor requirements so engineers can handle big designs efficiently, implement changes incrementally, and debug problems interactively. For large analyses, the Amber Analyzer leverages the power of threaded computing (multi-core, multi-CPU) to deliver the raw performance required for today's largest circuits. For small changes, it utilizes incremental technology to provide immediate feedback to the engineer without any compromise in accuracy. The base delay analysis is within one percent of other timing analysis tools, while the signal integrity analysis is within three percent of SPICE.

The Amber Analyzer is the first static timing and signal integrity tool that is fully threaded — from reading designs, to calculating delay and crosstalk, and generating reports. It delivers 10x to 20x performance improvements over existing solutions. Signal integrity analysis of a 10 million-instance design runs in two hours front-to-back on a four-CPU (8 cores total) system. On an eight-CPU system (16 cores total), the same design runs in slightly more than an hour. The performance of the Amber Analyzer scales linearly with the number of CPUs at least up through 64 cores.

The Amber Analyzer is fully incremental across all classes of analysis (timing, signal integrity, leakage) with any type of design change: cells swaps, netlist modifications, constraints, or parasitics. A 50,000-cell swap on the same 10 million-instance design takes less than three minutes to analyze for signal integrity. The Amber incremental capability guarantees that designers will get exactly the same answer as if they had run entire design flat. Moreover, the memory footprint for the analysis is proportional to the change. Incremental analysis can be run with desktop class machines.

The Amber Analyzer delivers the functionality designers have been asking for in static analysis solutions. It is inherently multi-corner and multi-mode so timing and signal integrity can be analyzed across all operating conditions simultaneously. It has a persistent database for the design and analysis results. It provides an experiment layer that allows multiple users to interact and debug timing results and perform what-if analysis and diagnostics. It features an open C-based application programming interface (API) that allows users to incorporate the Amber platform into their own tools or to develop specialized tools or optimizers. Finally, it is fully compatible with existing scripts, design flows, and libraries.

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