Averant is a startup electronic design automation (EDA) company focusing on verification of complex ICs and digital intellectual property (IP). The continuing growth in design complexity has caused a functional gap between what can be built and what can be verified before production. Finding mistakes after production can cost hundreds of millions of dollars, as seen with the Intel Pentium and the Toshiba floppy disk controller bugs. Averant closes the functional verification gap by delivering a new static verification technology that guarantees blocks used in design are functionally correct before production.

Averant's customers are leading companies in the internet networking, personal computing, telecommunications, and graphics areas. These include such firms as ARM, Toshiba, Cypress, Canon, ATI, Hitachi, and NEC.

Because of the increase in design complexity, verification of chip designs is being severely strained using the currently popular vector-based simulation approach. To solve this problem, Averant offers the EDA industry's first static functional verification tool. Targeted to RTL designers, architects, and validation engineers building ASICs, IP cores, and programmable parts, Solidify verifies that the intended behavior found in their functional specifications is correctly coded into a hardware description language (HDL). Averant's products make RTL design easier by delivering a breakthrough in debugging speed, capacity, and ease-of-use at the start of the design cycle where coding and verification first occur.

Averant's Solidify(TM) tool delivers unprecedented performance in block-level verification for RTL designers. Solidify improves design quality, shortens design cycles, and eliminates unnecessary simulation. Averant's products are easily incorporated into synthesis and IP reuse design flows.

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