VRM Overview
Design teams focus their energy primarily on one system-level configuration, and suffer through the inefficiencies of finding and resolving simple block-level and subsystem design bugs in slow and unwieldy system-level simulation. To resolve this problem, designers need to quickly build up rigorous verification configurations from reusable verification models. This would simplify the creation of verification environments for designs at any level of integration, and would allow distinct block-level and system-level verification environments to be developed quickly with minimum overhead and maximum consistency. Such a strategy in the verification space would be parallel to the way that today's systems (System on a Chip or SoC) are built from individual IP design components. Beyond reuse, designers also need ways to get more functional verification value in less simulation time and to simplify and reduce the amount of code needed to create a specific test case. This article identifies a methodology to achieve these goals by modularizing the verification environment.
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