Verifying Virtual Components and VC-Based SoC Designs

This paper is an overview of issues related to the verification of both VCs and of VC-based chips. The focus is on functional verification; topics include behavioral testbenches, interface protocol monitors, test vector replay and capture of designer intent. It also discusses the relationship between VC verification and VC test, especially for SoC designs that incorporate on-chip buses to connect multiple VCs.

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