Ultra High Performance Image Processing Architectures For Hardware-In-The-Loop Testing

Synthetic scene generation systems require huge computational resources to operate on potentially large data sets of information and to interface to advanced sensor technology via current scene projectors. Nallatech Ltd has been focused in the area of low latency hardware and algorithm development for many years. In collaboration with Matra British Aerospace Dynamics UK (MBDUK), (Reference SPIE '96 2741-13), minimum latency systems have already been developed offering latency of only several video lines in 3D target scene generation systems.

The rapid progression of FPGAs towards 1 Million gate devices together with the ever increasing performance of today's DSPs have allowed Nallatech to formulate an architecture that is particularly suited to HWIL systems.

This paper is presented in two sections:

Nallatech will discuss these new architectures and show the specific performance advantages for HWIL applications of these concepts over conventional processor architectures. This is aimed at supporting IR seeker and tracker HWIL systems proving with scene projection at 1024x1024 pixels, over 100Hz frame rates, less than 1 frame latency, with 16 bits per pixel, and 4x oversampling simultaneously.

MBDUK is proceeding on upgrading existing target scene generation facilities to this latest architecture. A description of the target, radiance and atmospheric modeling complexity will be presented along with a novel method of exhaust plume and flare modeling using the particle method. Simulations of several thousand particles will be demonstrated providing realistic signatures in terms of spatial dynamics and IR radiance.

View Entire Paper | Previous Page | White Papers Search

If you found this page useful, bookmark and share it on: